Unverified Commit ce1daeeb authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
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riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree 



The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent bf6279b3

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -27,7 +27,8 @@ cpu0: cpu@0 { 
			riscv,isa = "rv64imafdc";

			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm";

					       "zifencei", "zihpm", "xtheadvector";

			thead,vlenb = <128>;

			#cooling-cells = <2>;



			cpu0_intc: interrupt-controller {