Commit 9f98b429 authored by Baihan Li's avatar Baihan Li Committed by Dmitry Baryshkov
Browse files

drm/hisilicon/hibmc: fix rare monitors cannot display problem 



In some case, the dp link training success at 8.1Gbps, but the sink's
maximum supported rate is less than 8.1G. So change the default 8.1Gbps
link rate to the rate that reads from devices' capabilities.

Fixes: 54063d86 ("drm/hisilicon/hibmc: add dp link moduel in hibmc drivers")
Signed-off-by: default avatarBaihan Li <libaihan@huawei.com>
Signed-off-by: default avatarYongbang Shi <shiyongbang@huawei.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250813094238.3722345-6-shiyongbang@huawei.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent 93a08f85

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

+12 −2
Original line number Diff line number Diff line
@@ -325,6 +325,17 @@ static int hibmc_dp_link_downgrade_training_eq(struct hibmc_dp_dev *dp) 
	return hibmc_dp_link_reduce_rate(dp);

}



static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp)

{

	dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE];

	if (dp->link.cap.link_rate > DP_LINK_BW_8_1 || !dp->link.cap.link_rate)

		dp->link.cap.link_rate = DP_LINK_BW_8_1;



	dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

	if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX)

		dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX;

}



int hibmc_dp_link_training(struct hibmc_dp_dev *dp)

{

	struct hibmc_dp_link *link = &dp->link;
@@ -334,8 +345,7 @@ int hibmc_dp_link_training(struct hibmc_dp_dev *dp) 
	if (ret)

		drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret);



	dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE];

	dp->link.cap.lanes = 0x2;

	hibmc_dp_update_caps(dp);



	ret = hibmc_dp_get_serdes_rate_cfg(dp);

	if (ret < 0)