Commit 9fd5aa5a authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: remove GC and IGC related code from dpu catalog 



Gamma Correction (GC) and Inverse Gamma Correction(IGC) is
currently unused. In addition dpu_dspp_sub_blks didn't even have an igc
member describing the block.

Drop related code from the dpu hardware catalog otherwise this becomes a
burden to carry across chipsets in the catalog.

changes in v3:
	- drop IGC related code from dpu_hw_catalog too
	- update commit text accordingly

Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/534725/
Link: https://lore.kernel.org/r/20230428223646.23595-3-quic_abhinavk@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 7debb6bb

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+1 −3
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ 


#define MERGE_3D_SM8150_MASK (0)



#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)

#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC)



#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
@@ -449,8 +449,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 
static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {

	.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,

		.len = 0x90, .version = 0x10007},

	.gc = { .id = DPU_DSPP_GC, .base = 0x17c0,

		.len = 0x90, .version = 0x10007},

};



static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+0 −10
Original line number Diff line number Diff line
@@ -127,13 +127,9 @@ enum { 
/**

 * DSPP sub-blocks

 * @DPU_DSPP_PCC             Panel color correction block

 * @DPU_DSPP_GC              Gamma correction block

 * @DPU_DSPP_IGC             Inverse gamma correction block

 */

enum {

	DPU_DSPP_PCC = 0x1,

	DPU_DSPP_GC,

	DPU_DSPP_IGC,

	DPU_DSPP_MAX

};
@@ -398,7 +394,6 @@ struct dpu_caps { 
 * @hsic:

 * @memcolor:

 * @pcc_blk:

 * @igc_blk:

 * @format_list: Pointer to list of supported formats

 * @num_formats: Number of supported formats

 * @virt_format_list: Pointer to list of supported formats for virtual planes
@@ -419,7 +414,6 @@ struct dpu_sspp_sub_blks { 
	struct dpu_pp_blk hsic_blk;

	struct dpu_pp_blk memcolor_blk;

	struct dpu_pp_blk pcc_blk;

	struct dpu_pp_blk igc_blk;



	const u32 *format_list;

	u32 num_formats;
@@ -433,22 +427,18 @@ struct dpu_sspp_sub_blks { 
 * @maxwidth:               Max pixel width supported by this mixer

 * @maxblendstages:         Max number of blend-stages supported

 * @blendstage_base:        Blend-stage register base offset

 * @gc: gamma correction block

 */

struct dpu_lm_sub_blks {

	u32 maxwidth;

	u32 maxblendstages;

	u32 blendstage_base[MAX_BLOCKS];

	struct dpu_pp_blk gc;

};



/**

 * struct dpu_dspp_sub_blks: Information of DSPP block

 * @gc : gamma correction block

 * @pcc: pixel color correction block

 */

struct dpu_dspp_sub_blks {

	struct dpu_pp_blk gc;

	struct dpu_pp_blk pcc;

};