Commit a08f0ac3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux into clk-sophgo 

Pull RISC-V Sophgo clk driver updates from Chen Wang:

 - Replace compatible for Sophgo CV1800 series SoC
 - Add clock support for Sophgo SG2044

* tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC
parents 0af2f6be 41b08610

Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml

+12 −4
Original line number Diff line number Diff line
@@ -11,10 +11,18 @@ maintainers: 


properties:

  compatible:

    enum:

      - sophgo,cv1800-clk

      - sophgo,cv1810-clk

    oneOf:

      - enum:

          - sophgo,cv1800b-clk

          - sophgo,cv1812h-clk

          - sophgo,sg2000-clk

      - items:

          - const: sophgo,sg2002-clk

          - const: sophgo,sg2000-clk

      - const: sophgo,cv1800-clk

        deprecated: true

      - const: sophgo,cv1810-clk

        deprecated: true



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml

0 → 100644
+99 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2044 Clock Controller



maintainers:

  - Inochi Amaoto <inochiama@gmail.com>



description: |

  The Sophgo SG2044 clock controller requires an external oscillator

  as input clock.



  All available clocks are defined as preprocessor macros in

  include/dt-bindings/clock/sophgo,sg2044-clk.h



properties:

  compatible:

    const: sophgo,sg2044-clk



  reg:

    maxItems: 1



  clocks:

    items:

      - description: fpll0

      - description: fpll1

      - description: fpll2

      - description: dpll0

      - description: dpll1

      - description: dpll2

      - description: dpll3

      - description: dpll4

      - description: dpll5

      - description: dpll6

      - description: dpll7

      - description: mpll0

      - description: mpll1

      - description: mpll2

      - description: mpll3

      - description: mpll4

      - description: mpll5



  clock-names:

    items:

      - const: fpll0

      - const: fpll1

      - const: fpll2

      - const: dpll0

      - const: dpll1

      - const: dpll2

      - const: dpll3

      - const: dpll4

      - const: dpll5

      - const: dpll6

      - const: dpll7

      - const: mpll0

      - const: mpll1

      - const: mpll2

      - const: mpll3

      - const: mpll4

      - const: mpll5



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/sophgo,sg2044-pll.h>



    clock-controller@50002000 {

      compatible = "sophgo,sg2044-clk";

      reg = <0x50002000 0x1000>;

      #clock-cells = <1>;

      clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,

               <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,

               <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,

               <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,

               <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,

               <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,

               <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,

               <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,

               <&syscon CLK_MPLL5>;

      clock-names = "fpll0", "fpll1", "fpll2", "dpll0",

                    "dpll1", "dpll2", "dpll3", "dpll4",

                    "dpll5", "dpll6", "dpll7", "mpll0",

                    "mpll1", "mpll2", "mpll3", "mpll4",

                    "mpll5";

    };

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml

0 → 100644
+49 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2044 SoC TOP system controller



maintainers:

  - Inochi Amaoto <inochiama@gmail.com>



description:

  The Sophgo SG2044 TOP system controller is a hardware block grouping

  multiple small functions, such as clocks and some other internal

  function.



properties:

  compatible:

    items:

      - const: sophgo,sg2044-top-syscon

      - const: syscon



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    syscon@50000000 {

      compatible = "sophgo,sg2044-top-syscon", "syscon";

      reg = <0x50000000 0x1000>;

      #clock-cells = <1>;

      clocks = <&osc>;

    };

drivers/clk/sophgo/Kconfig

+19 −0
Original line number Diff line number Diff line
@@ -37,3 +37,22 @@ config CLK_SOPHGO_SG2042_RPGATE 
	  This clock IP depends on SG2042 Clock Generator because it uses

	  clock from Clock Generator IP as input.

	  This driver provides Gate function for RP.



config CLK_SOPHGO_SG2044

	tristate "Sophgo SG2044 clock controller support"

	depends on ARCH_SOPHGO || COMPILE_TEST

	help

	  This driver supports the clock controller on the Sophgo SG2044

	  SoC. This controller requires mulitple PLL clock as input.

	  This clock control provides PLL clocks and common clock function

	  for various IPs on the SoC.



config CLK_SOPHGO_SG2044_PLL

	tristate "Sophgo SG2044 PLL clock controller support"

	depends on ARCH_SOPHGO || COMPILE_TEST

	select MFD_SYSCON

	select REGMAP_MMIO

	help

	  This driver supports the PLL clock controller on the Sophgo

	  SG2044 SoC. This controller requires 25M oscillator as input.

	  This clock control provides PLL clocks on the SoC.

drivers/clk/sophgo/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -9,3 +9,5 @@ clk-sophgo-cv1800-y += clk-cv18xx-pll.o 
obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN)	+= clk-sg2042-clkgen.o

obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL)	+= clk-sg2042-pll.o

obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE)	+= clk-sg2042-rpgate.o

obj-$(CONFIG_CLK_SOPHGO_SG2044)		+= clk-sg2044.o

obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL)	+= clk-sg2044-pll.o