Commit a3156676 authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe: Implement recent spec updates to Wa_16025250150 



The hardware teams noticed that the originally documented workaround
steps for Wa_16025250150 may not be sufficient to fully avoid a hardware
issue.  The workaround documentation has been augmented to suggest
programming one additional register; make the corresponding change in
the driver.

Fixes: 7654d51f ("drm/xe/xe2hpg: Add Wa_16025250150")
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20260319-wa_16025250150_part2-v1-1-46b1de1a31b2@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent e8c3a913

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -578,6 +578,7 @@ 
#define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)

#define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)

#define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)

#define   L3_128B_256B_WRT_DIS			REG_BIT(40 - 32)

#define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)

#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)

#define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)

drivers/gpu/drm/xe/xe_wa.c

+2 −1
Original line number Diff line number Diff line
@@ -260,7 +260,8 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
				   LSN_DIM_Z_WGT_MASK,

				   LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |

				   LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |

				   LSN_DIM_Z_WGT(1)))

				   LSN_DIM_Z_WGT(1)),

			SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))

	},



	/* Xe3_LPG */