Unverified Commit a31ffd6e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of... 

Merge tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes

This pull request contains Broadcom ARM64-based SoCs Device Tree fixes
for 6.13, please pull the following:

- Willow corrects the L2 cache line size on the Raspberry Pi 5 (2712) to
  the correct value of 64 bytes

* tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5

Link: https://lore.kernel.org/r/20241217190547.868744-1-florian.fainelli@broadcom.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a61dae11 058387d9

arch/arm64/boot/dts/broadcom/bcm2712.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ cpu0: cpu@0 { 
			l2_cache_l0: l2-cache-l0 {

				compatible = "cache";

				cache-size = <0x80000>;

				cache-line-size = <128>;

				cache-line-size = <64>;

				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set

				cache-level = <2>;

				cache-unified;
@@ -91,7 +91,7 @@ cpu1: cpu@1 { 
			l2_cache_l1: l2-cache-l1 {

				compatible = "cache";

				cache-size = <0x80000>;

				cache-line-size = <128>;

				cache-line-size = <64>;

				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set

				cache-level = <2>;

				cache-unified;
@@ -115,7 +115,7 @@ cpu2: cpu@2 { 
			l2_cache_l2: l2-cache-l2 {

				compatible = "cache";

				cache-size = <0x80000>;

				cache-line-size = <128>;

				cache-line-size = <64>;

				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set

				cache-level = <2>;

				cache-unified;
@@ -139,7 +139,7 @@ cpu3: cpu@3 { 
			l2_cache_l3: l2-cache-l3 {

				compatible = "cache";

				cache-size = <0x80000>;

				cache-line-size = <128>;

				cache-line-size = <64>;

				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set

				cache-level = <2>;

				cache-unified;