Unverified Commit a46a9cd1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.20-tag1' of... 

Merge tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
   Renesas RZ/T21H and RZ/N2H
 - Add DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks
   and resets on Renesas RZ/V2N
 - Add more serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N

* tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g056: Add clock and reset entries for TSU
  clk: renesas: r9a09g057: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add entries for ICU
  clk: renesas: r9a09g056: Add entries for the DMACs
  clk: renesas: r9a09g077: Propagate rate changes through mux parents
  clk: renesas: r9a09g077: Add xSPI core and module clocks
  clk: renesas: rzg2l: Select correct div round macro
  clk: renesas: rzg2l: Fix intin variable size
  dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs
parents 8f0b4cce ebb3acf4

drivers/clk/renesas/r9a09g056-cpg.c

+178 −0
Original line number Diff line number Diff line
@@ -46,11 +46,16 @@ enum clk_ids { 
	CLK_PLLCLN_DIV2,

	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLCLN_DIV64,

	CLK_PLLCLN_DIV256,

	CLK_PLLCLN_DIV1024,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV8,

	CLK_PLLDTY_DIV16,

	CLK_PLLDTY_RCPU,

	CLK_PLLDTY_RCPU_DIV4,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_ISP,
@@ -178,12 +183,17 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),

	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),

	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),

	DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),

	DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),

	DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),

	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
@@ -231,6 +241,18 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
};



static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {

	DEF_MOD("dmac_0_aclk",			CLK_PLLCM33_GEAR, 0, 0, 0, 0,

						BUS_MSTOP(5, BIT(9))),

	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,

						BUS_MSTOP(3, BIT(2))),

	DEF_MOD("dmac_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,

						BUS_MSTOP(3, BIT(3))),

	DEF_MOD("dmac_3_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,

						BUS_MSTOP(10, BIT(11))),

	DEF_MOD("dmac_4_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,

						BUS_MSTOP(10, BIT(12))),

	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,

						BUS_MSTOP_NONE),

	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,

						BUS_MSTOP(3, BIT(5))),

	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3,
@@ -265,6 +287,124 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps3_n",		CLK_PLLCLN_DIV1024, 5, 15, 2, 31,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 0, 3, 0,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 1, 3, 1,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci1_pclk",			CLK_PLLCLN_DIV16, 6, 2, 3, 2,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_tclk",			CLK_PLLCLN_DIV16, 6, 3, 3, 3,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 4, 3, 4,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 5, 3, 5,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 6, 3, 6,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci2_pclk",			CLK_PLLCLN_DIV16, 6, 7, 3, 7,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_tclk",			CLK_PLLCLN_DIV16, 6, 8, 3, 8,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 9, 3, 9,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 10, 3, 10,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 11, 3, 11,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci3_pclk",			CLK_PLLCLN_DIV16, 6, 12, 3, 12,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_tclk",			CLK_PLLCLN_DIV16, 6, 13, 3, 13,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 14, 3, 14,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 15, 3, 15,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 0, 3, 16,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci4_pclk",			CLK_PLLCLN_DIV16, 7, 1, 3, 17,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_tclk",			CLK_PLLCLN_DIV16, 7, 2, 3, 18,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 3, 3, 19,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 4, 3, 20,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 5, 3, 21,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci5_pclk",			CLK_PLLCLN_DIV16, 7, 6, 3, 22,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_tclk",			CLK_PLLCLN_DIV16, 7, 7, 3, 23,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 8, 3, 24,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 9, 3, 25,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 10, 3, 26,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci6_pclk",			CLK_PLLCLN_DIV16, 7, 11, 3, 27,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_tclk",			CLK_PLLCLN_DIV16, 7, 12, 3, 28,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 13, 3, 29,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 14, 3, 30,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 15, 3, 31,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci7_pclk",			CLK_PLLCLN_DIV16, 8, 0, 4, 0,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_tclk",			CLK_PLLCLN_DIV16, 8, 1, 4, 1,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 2, 4, 2,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 3, 4, 3,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 4, 4, 4,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci8_pclk",			CLK_PLLCLN_DIV16, 8, 5, 4, 5,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_tclk",			CLK_PLLCLN_DIV16, 8, 6, 4, 6,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 7, 4, 7,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 8, 4, 8,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 9, 4, 9,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci9_pclk",			CLK_PLLCLN_DIV16, 8, 10, 4, 10,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_tclk",			CLK_PLLCLN_DIV16, 8, 11, 4, 11,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 12, 4, 12,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 13, 4, 13,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -397,10 +537,20 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,

						BUS_MSTOP(5, BIT(2))),

	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,

						BUS_MSTOP(2, BIT(15))),

};



static const struct rzv2h_reset r9a09g056_resets[] __initconst = {

	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */

	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */

	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */

	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */

	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */

	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */

	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */

	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */

	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */

	DEF_RST(6, 13, 2, 30),		/* GTM_0_PRESETZ */
@@ -415,6 +565,32 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */

	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */

	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */

	DEF_RST(8, 4, 3, 21),		/* RSCI1_TRESETN */

	DEF_RST(8, 5, 3, 22),		/* RSCI2_PRESETN */

	DEF_RST(8, 6, 3, 23),		/* RSCI2_TRESETN */

	DEF_RST(8, 7, 3, 24),		/* RSCI3_PRESETN */

	DEF_RST(8, 8, 3, 25),		/* RSCI3_TRESETN */

	DEF_RST(8, 9, 3, 26),		/* RSCI4_PRESETN */

	DEF_RST(8, 10, 3, 27),		/* RSCI4_TRESETN */

	DEF_RST(8, 11, 3, 28),		/* RSCI5_PRESETN */

	DEF_RST(8, 12, 3, 29),		/* RSCI5_TRESETN */

	DEF_RST(8, 13, 3, 30),		/* RSCI6_PRESETN */

	DEF_RST(8, 14, 3, 31),		/* RSCI6_TRESETN */

	DEF_RST(8, 15, 4, 0),		/* RSCI7_PRESETN */

	DEF_RST(9, 0, 4, 1),		/* RSCI7_TRESETN */

	DEF_RST(9, 1, 4, 2),		/* RSCI8_PRESETN */

	DEF_RST(9, 2, 4, 3),		/* RSCI8_TRESETN */

	DEF_RST(9, 3, 4, 4),		/* RSCI9_PRESETN */

	DEF_RST(9, 4, 4, 5),		/* RSCI9_TRESETN */

	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */

	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */

	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */

	DEF_RST(7, 14, 3, 15),		/* RSPI_1_TRESETN */

	DEF_RST(7, 15, 3, 16),		/* RSPI_2_PRESETN */

	DEF_RST(8, 0, 3, 17),		/* RSPI_2_TRESETN */

	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */

	DEF_RST(9, 6, 4, 7),		/* I3C_0_PRESETN */

	DEF_RST(9, 7, 4, 8),		/* I3C_0_TRESETN */
@@ -454,6 +630,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */

	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */

	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */

};



const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {

drivers/clk/renesas/r9a09g057-cpg.c

+126 −0
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ enum clk_ids { 
	CLK_PLLCLN_DIV2,

	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLCLN_DIV64,

	CLK_PLLCLN_DIV256,

	CLK_PLLCLN_DIV1024,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,
@@ -182,6 +185,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),

	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),

	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),

	DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),

	DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),

	DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -288,6 +294,106 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps3_n",		CLK_PLLCLN_DIV1024, 5, 15, 2, 31,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 0, 3, 0,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 1, 3, 1,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci1_pclk",			CLK_PLLCLN_DIV16, 6, 2, 3, 2,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_tclk",			CLK_PLLCLN_DIV16, 6, 3, 3, 3,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 4, 3, 4,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 5, 3, 5,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 6, 3, 6,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci2_pclk",			CLK_PLLCLN_DIV16, 6, 7, 3, 7,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_tclk",			CLK_PLLCLN_DIV16, 6, 8, 3, 8,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 9, 3, 9,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 10, 3, 10,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 11, 3, 11,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci3_pclk",			CLK_PLLCLN_DIV16, 6, 12, 3, 12,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_tclk",			CLK_PLLCLN_DIV16, 6, 13, 3, 13,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 14, 3, 14,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 15, 3, 15,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 0, 3, 16,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci4_pclk",			CLK_PLLCLN_DIV16, 7, 1, 3, 17,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_tclk",			CLK_PLLCLN_DIV16, 7, 2, 3, 18,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 3, 3, 19,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 4, 3, 20,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 5, 3, 21,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci5_pclk",			CLK_PLLCLN_DIV16, 7, 6, 3, 22,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_tclk",			CLK_PLLCLN_DIV16, 7, 7, 3, 23,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 8, 3, 24,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 9, 3, 25,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 10, 3, 26,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci6_pclk",			CLK_PLLCLN_DIV16, 7, 11, 3, 27,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_tclk",			CLK_PLLCLN_DIV16, 7, 12, 3, 28,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 13, 3, 29,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 14, 3, 30,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 15, 3, 31,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci7_pclk",			CLK_PLLCLN_DIV16, 8, 0, 4, 0,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_tclk",			CLK_PLLCLN_DIV16, 8, 1, 4, 1,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 2, 4, 2,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 3, 4, 3,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 4, 4, 4,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci8_pclk",			CLK_PLLCLN_DIV16, 8, 5, 4, 5,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_tclk",			CLK_PLLCLN_DIV16, 8, 6, 4, 6,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 7, 4, 7,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 8, 4, 8,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 9, 4, 9,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci9_pclk",			CLK_PLLCLN_DIV16, 8, 10, 4, 10,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_tclk",			CLK_PLLCLN_DIV16, 8, 11, 4, 11,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 12, 4, 12,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 13, 4, 13,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,

						BUS_MSTOP(3, BIT(11) | BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,
@@ -488,6 +594,26 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */

	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */

	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */

	DEF_RST(8, 4, 3, 21),		/* RSCI1_TRESETN */

	DEF_RST(8, 5, 3, 22),		/* RSCI2_PRESETN */

	DEF_RST(8, 6, 3, 23),		/* RSCI2_TRESETN */

	DEF_RST(8, 7, 3, 24),		/* RSCI3_PRESETN */

	DEF_RST(8, 8, 3, 25),		/* RSCI3_TRESETN */

	DEF_RST(8, 9, 3, 26),		/* RSCI4_PRESETN */

	DEF_RST(8, 10, 3, 27),		/* RSCI4_TRESETN */

	DEF_RST(8, 11, 3, 28),		/* RSCI5_PRESETN */

	DEF_RST(8, 12, 3, 29),		/* RSCI5_TRESETN */

	DEF_RST(8, 13, 3, 30),		/* RSCI6_PRESETN */

	DEF_RST(8, 14, 3, 31),		/* RSCI6_TRESETN */

	DEF_RST(8, 15, 4, 0),		/* RSCI7_PRESETN */

	DEF_RST(9, 0, 4, 1),		/* RSCI7_TRESETN */

	DEF_RST(9, 1, 4, 2),		/* RSCI8_PRESETN */

	DEF_RST(9, 2, 4, 3),		/* RSCI8_TRESETN */

	DEF_RST(9, 3, 4, 4),		/* RSCI9_PRESETN */

	DEF_RST(9, 4, 4, 5),		/* RSCI9_TRESETN */

	DEF_RST(7, 9, 3, 10),		/* RTC_0_RST_RTC */

	DEF_RST(7, 10, 3, 11),		/* RTC_0_RST_RTC_V */

	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */

drivers/clk/renesas/r9a09g077-cpg.c

+191 −4

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/renesas/rzg2l-cpg.c

+3 −3
Original line number Diff line number Diff line
@@ -122,8 +122,8 @@ struct div_hw_data { 


struct rzg2l_pll5_param {

	u32 pl5_fracin;

	u16 pl5_intin;

	u8 pl5_refdiv;

	u8 pl5_intin;

	u8 pl5_postdiv1;

	u8 pl5_postdiv2;

	u8 pl5_spread;
@@ -572,7 +572,7 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, 
	foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,

					   (params->pl5_intin << 24) + params->pl5_fracin),

			       params->pl5_refdiv) >> 24;

	foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate,

	foutpostdiv_rate = DIV_ROUND_CLOSEST(foutvco_rate,

					     params->pl5_postdiv1 * params->pl5_postdiv2);



	return foutpostdiv_rate;

include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

+2 −0
Original line number Diff line number Diff line
@@ -31,5 +31,7 @@ 
#define R9A09G077_ETCLKC		19

#define R9A09G077_ETCLKD		20

#define R9A09G077_ETCLKE		21

#define R9A09G077_XSPI_CLK0		22

#define R9A09G077_XSPI_CLK1		23



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */