Commit a4dcb2f8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-next 

 - Update Zynqmp driver for Versal NET platforms
 - Add clk driver for Versal clocking wizard IP

* clk-zynq:
  drivers: clk: zynqmp: update divider round rate logic
  drivers: clk: zynqmp: calculate closest mux rate

* clk-xilinx:
  clocking-wizard: Add support for versal clocking wizard
  dt-bindings: clock: xilinx: add versal compatible

* clk-stm:
  dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform
  clk: stm32mp1: use stm32mp13 reset driver
  clk: stm32mp1: move stm32mp1 clock driver into stm32 directory
parents 23bd8c4a 1fe15be1 3a96393a b5be49db

Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STM32MP25 Reset Clock Controller



maintainers:

  - Gabriel Fernandez <gabriel.fernandez@foss.st.com>



description: |

  The RCC hardware block is both a reset and a clock controller.

  RCC makes also power management (resume/supend).



  See also::

    include/dt-bindings/clock/st,stm32mp25-rcc.h

    include/dt-bindings/reset/st,stm32mp25-rcc.h



properties:

  compatible:

    enum:

      - st,stm32mp25-rcc



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  clocks:

    items:

      - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)

      - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)

      - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)

      - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)

      - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)



  clock-names:

    items:

      - const: hse

      - const: hsi

      - const: msi

      - const: lse

      - const: lsi



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/st,stm32mp25-rcc.h>



    rcc: clock-controller@44200000 {

        compatible = "st,stm32mp25-rcc";

        reg = <0x44200000 0x10000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        clock-names = "hse", "hsi", "msi", "lse", "lsi";

        clocks = <&scmi_clk CK_SCMI_HSE>,

                 <&scmi_clk CK_SCMI_HSI>,

                 <&scmi_clk CK_SCMI_MSI>,

                 <&scmi_clk CK_SCMI_LSE>,

                 <&scmi_clk CK_SCMI_LSI>;

    };

...

Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml

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@@ -20,6 +20,7 @@ properties: 
      - xlnx,clocking-wizard

      - xlnx,clocking-wizard-v5.2

      - xlnx,clocking-wizard-v6.0

      - xlnx,versal-clk-wizard





  reg:

drivers/clk/Kconfig

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@@ -414,16 +414,6 @@ config COMMON_CLK_VC7 
	  Renesas Versaclock7 is a family of configurable clock generator

	  and jitter attenuator ICs with fractional and integer dividers.



config COMMON_CLK_STM32MP135

	def_bool COMMON_CLK && MACH_STM32MP13

	help

	  Support for stm32mp135 SoC family clocks



config COMMON_CLK_STM32MP157

	def_bool COMMON_CLK && MACH_STM32MP157

	help

	  Support for stm32mp157 SoC family clocks



config COMMON_CLK_STM32F

	def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)

	help
@@ -504,6 +494,7 @@ source "drivers/clk/starfive/Kconfig" 
source "drivers/clk/sunxi/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

source "drivers/clk/tegra/Kconfig"

source "drivers/clk/stm32/Kconfig"

source "drivers/clk/ti/Kconfig"

source "drivers/clk/uniphier/Kconfig"

source "drivers/clk/visconti/Kconfig"

drivers/clk/Makefile

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@@ -70,7 +70,6 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o 
obj-$(CONFIG_COMMON_CLK_SP7021)		+= clk-sp7021.o

obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o

obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o

obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o

obj-$(CONFIG_COMMON_CLK_TPS68470)      += clk-tps68470.o

obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o

obj-$(CONFIG_CLK_TWL)			+= clk-twl.o

drivers/clk/stm32/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only

# common clock support for STMicroelectronics SoC family.



menuconfig COMMON_CLK_STM32MP

	bool "Clock support for common STM32MP clocks"

	depends on ARCH_STM32 || COMPILE_TEST

	default y

	select RESET_CONTROLLER

	help

	  Support for STM32MP SoC family clocks.



if COMMON_CLK_STM32MP



config COMMON_CLK_STM32MP135

	bool "Clock driver for stm32mp13x clocks"

	depends on ARM || COMPILE_TEST

	default y

	help

	  Support for stm32mp13x SoC family clocks.



config COMMON_CLK_STM32MP157

	bool "Clock driver for stm32mp15x clocks"

	depends on ARM || COMPILE_TEST

	default y

	help

	  Support for stm32mp15x SoC family clocks.



endif