Commit a6db1993 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix some non-initialized register mask and setting 



[why]
fix some non-initialized register mask and update golden setting

Reviewed-by: default avatarDuncan Ma <duncan.ma@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c06ef68a

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+42 −14
Original line number Diff line number Diff line
@@ -53,6 +53,14 @@ 
#define mmCLK1_CLK3_DFS_CNTL                            0x16E72

#define mmCLK1_CLK4_DFS_CNTL                            0x16E75



#define mmCLK1_CLK0_CURRENT_CNT                         0x16EE7

#define mmCLK1_CLK1_CURRENT_CNT                         0x16EE8

#define mmCLK1_CLK2_CURRENT_CNT                         0x16EE9

#define mmCLK1_CLK3_CURRENT_CNT                         0x16EEA

#define mmCLK1_CLK4_CURRENT_CNT                         0x16EEB



#define mmCLK4_CLK0_CURRENT_CNT                         0x1B0C9



#define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffUL

#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000UL

#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000UL
@@ -452,6 +460,26 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) 


static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr_internal *clk_mgr)

{

    unsigned int dispclk_khz_reg    = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK

    unsigned int dppclk_khz_reg     = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK

    unsigned int dprefclk_khz_reg   = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK

    unsigned int dcfclk_khz_reg     = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK

    unsigned int dtbclk_khz_reg     = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK

    unsigned int fclk_khz_reg       = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK



    // Overrides for these clocks in case there is no p_state change support

    int dramclk_khz_override = new_clocks->dramclk_khz;

    int fclk_khz_override = new_clocks->fclk_khz;



    int num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;



    if (!new_clocks->p_state_change_support) {

	    dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;

    }

    if (!new_clocks->fclk_p_state_change_support) {

	    fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;

    }



	////////////////////////////////////////////////////////////////////////////

	//	IMPORTANT: 	When adding more clocks to these logs, do NOT put a newline

	//	 			anywhere other than at the very end of the string.
@@ -466,20 +494,20 @@ static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr 
		new_clocks->dcfclk_khz > 0 &&

		new_clocks->dppclk_khz > 0) {



		if (new_clocks->p_state_change_support) {

			DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:%d - fclk_khz:%d - "

						 "dcfclk_khz:%d - dppclk_khz:%d\n",

						 new_clocks->dramclk_khz,

						 new_clocks->fclk_khz,

		DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "

			"dcfclk:%d - dppclk:%d - dispclk_hw:%d - "

			"dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "

			"dtbclk_hw:%d - fclk_hw:%d\n",

			dramclk_khz_override,

			fclk_khz_override,

			new_clocks->dcfclk_khz,

						 new_clocks->dppclk_khz);

		} else {

			DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:1249000 - fclk_khz:%d - "

						 "dcfclk_khz:%d - dppclk_khz:%d\n",

						 new_clocks->fclk_khz,

						 new_clocks->dcfclk_khz,

						 new_clocks->dppclk_khz);

		}

			new_clocks->dppclk_khz,

			dispclk_khz_reg,

			dppclk_khz_reg,

			dprefclk_khz_reg,

			dcfclk_khz_reg,

			dtbclk_khz_reg,

			fclk_khz_reg);

	}

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+4 −1
Original line number Diff line number Diff line
@@ -577,7 +577,10 @@ struct dcn10_stream_enc_registers { 
	type DIG_FIFO_READ_START_LEVEL;\

	type DIG_FIFO_ENABLE;\

	type DIG_FIFO_RESET;\

	type DIG_FIFO_RESET_DONE

	type DIG_FIFO_RESET_DONE;\

	type PIXEL_ENCODING_TYPE;\

	type UNCOMPRESSED_PIXEL_FORMAT;\

	type UNCOMPRESSED_COMPONENT_DEPTH



#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \

	type DIG_FE_CLK_EN;\

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

+4 −2
Original line number Diff line number Diff line
@@ -45,11 +45,12 @@ 


struct dcn3_clk_internal {

	int dummy;

	/*TODO:

//	TODO:

	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk

	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk

	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk

	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk

	uint32_t CLK1_CLK4_CURRENT_CNT;

	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider

	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
@@ -57,7 +58,8 @@ struct dcn3_clk_internal { 
	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass

	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass

	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

	*/



	uint32_t CLK4_CLK0_CURRENT_CNT; //fclk

};



struct dcn301_clk_internal {

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

+15 −1
Original line number Diff line number Diff line
@@ -163,7 +163,13 @@ enum dentist_divider_range { 
	CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \

	CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \

	CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \

	CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)

	CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \

    CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \

    CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \

    CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \

    CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \

    CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \

    CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT)



#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \

	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
@@ -222,6 +228,8 @@ struct clk_mgr_registers { 
	uint32_t CLK4_CLK2_CURRENT_CNT;

	uint32_t CLK4_CLK_PLL_REQ;



	uint32_t CLK4_CLK0_CURRENT_CNT;



	uint32_t CLK3_CLK2_DFS_CNTL;

	uint32_t CLK3_CLK_PLL_REQ;
@@ -235,6 +243,12 @@ struct clk_mgr_registers { 
	uint32_t CLK1_CLK3_DFS_CNTL;

	uint32_t CLK1_CLK4_DFS_CNTL;



	uint32_t CLK1_CLK0_CURRENT_CNT;

    uint32_t CLK1_CLK1_CURRENT_CNT;

    uint32_t CLK1_CLK2_CURRENT_CNT;

    uint32_t CLK1_CLK3_CURRENT_CNT;

    uint32_t CLK1_CLK4_CURRENT_CNT;



	uint32_t CLK0_CLK0_DFS_CNTL;

	uint32_t CLK0_CLK1_DFS_CNTL;

	uint32_t CLK0_CLK3_DFS_CNTL;