Commit a7719b2d authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a09g056: Add PCIe clocks and reset 



Add clocks and reset entries for the PCIe controller.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260312111521.115392-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 24a51f8b

drivers/clk/renesas/r9a09g056-cpg.c

+5 −0
Original line number Diff line number Diff line
@@ -505,6 +505,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,

						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("pcie_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,

						BUS_MSTOP(1, BIT(15))),

	DEF_MOD("pcie_0_clk_pmu",		CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,

						BUS_MSTOP(1, BIT(15))),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -628,6 +632,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(11, 2, 5, 3),		/* PCIE_0_ARESETN */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */

	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */