Commit ab558870 authored by Clément Léger's avatar Clément Léger Committed by Jakub Kicinski
Browse files

dt-bindings: net: renesas,rzn1-gmac: Document RZ/N1 GMAC support 



The RZ/N1 series of MPUs feature up to two Gigabit Ethernet controllers.
These controllers are based on Synopsys IPs. They can be connected to
RZ/N1 RGMII/RMII converters.

Add a binding that describes these GMAC devices.

Signed-off-by: default avatarClément Léger <clement.leger@bootlin.com>
[rgantois: commit log]
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarRomain Gantois <romain.gantois@bootlin.com>
Link: https://lore.kernel.org/r/20240513-rzn1-gmac1-v7-1-6acf58b5440d@bootlin.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 486ffc33

Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas GMAC



maintainers:

  - Romain Gantois <romain.gantois@bootlin.com>



select:

  properties:

    compatible:

      contains:

        enum:

          - renesas,r9a06g032-gmac

          - renesas,rzn1-gmac

  required:

    - compatible



allOf:

  - $ref: snps,dwmac.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a06g032-gmac

      - const: renesas,rzn1-gmac

      - const: snps,dwmac



  pcs-handle:

    description:

      phandle pointing to a PCS sub-node compatible with

      renesas,rzn1-miic.yaml#



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a06g032-sysctrl.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    ethernet@44000000 {

      compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";

      reg = <0x44000000 0x2000>;

      interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

      clock-names = "stmmaceth";

      clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;

      power-domains = <&sysctrl>;

      snps,multicast-filter-bins = <256>;

      snps,perfect-filter-entries = <128>;

      tx-fifo-depth = <2048>;

      rx-fifo-depth = <4096>;

      pcs-handle = <&mii_conv1>;

      phy-mode = "mii";

    };



...