Unverified Commit ab63e991 authored by Tim Kuo's avatar Tim Kuo Committed by Mark Brown
Browse files

spi: mt65xx: add dual and quad mode for standard spi device 



Mediatek SPI hardware natively supports dual and quad modes, and these
modes are already enabled for SPI flash devices under spi-mem framework
in MTK SPI controller spi-mt65xx. However, other SPI devices, such as
touch panels, are limited to single mode because spi-mt65xx lacks SPI
mode argument parsing from SPI framework for these SPI devices outside
spi-mem framework.

This patch adds dual and quad mode support for these SPI devices by
introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing.

Signed-off-by: default avatarTim Kuo <Tim.Kuo@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20250917055839.500615-1-Tim.Kuo@mediatek.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b28a55db

drivers/spi/spi-mt65xx.c

+25 −3
Original line number Diff line number Diff line
@@ -563,6 +563,22 @@ static void mtk_spi_setup_packet(struct spi_controller *host) 
	writel(reg_val, mdata->base + SPI_CFG1_REG);

}



inline u32 mtk_spi_set_nbit(u32 nbit)

{

	switch (nbit) {

	default:

		pr_warn_once("unknown nbit mode %u. Falling back to single mode\n",

			     nbit);

		fallthrough;

	case SPI_NBITS_SINGLE:

		return 0x0;

	case SPI_NBITS_DUAL:

		return 0x1;

	case SPI_NBITS_QUAD:

		return 0x2;

	}

}



static void mtk_spi_enable_transfer(struct spi_controller *host)

{

	u32 cmd;
@@ -729,10 +745,16 @@ static int mtk_spi_transfer_one(struct spi_controller *host, 


	/* prepare xfer direction and duplex mode */

	if (mdata->dev_comp->ipm_design) {

		if (!xfer->tx_buf || !xfer->rx_buf) {

		if (xfer->tx_buf && xfer->rx_buf) {

			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN;

		} else if (xfer->tx_buf) {

			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;

			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;

			reg_val |= mtk_spi_set_nbit(xfer->tx_nbits);

		} else {

			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;

			if (xfer->rx_buf)

			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;

			reg_val |= mtk_spi_set_nbit(xfer->rx_nbits);

		}

		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);

	}