Unverified Commit b28a55db authored by Mark Brown's avatar Mark Brown
Browse files

Miscellaneous fixes and clean-ups 

Merge series from Santhosh Kumar K <s-k6@ti.com>:

This series introduces some small but important fixes and cleanups in
the Cadence QSPI Controller.

Tested on TI's AM62A SK and AM62P SK:
Logs: https://gist.github.com/santhosh21/0d25767b58d9a1d9624f2c502dd8f36b
parents 18dda9eb d9e33b38

drivers/spi/spi-cadence-quadspi.c

+21 −13
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi) 
{

	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);



	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);

	return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB);

}



static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
@@ -571,7 +571,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 
		reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)

		     << CQSPI_REG_CMDCTRL_DUMMY_LSB;



	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);

	reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB);



	/* 0 means 1 byte. */

	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
@@ -579,7 +579,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 


	/* setup ADDR BIT field */

	if (op->addr.nbytes) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= ((op->addr.nbytes - 1) &

			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
@@ -646,7 +646,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 
	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;



	if (op->addr.nbytes) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= ((op->addr.nbytes - 1) &

			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
@@ -655,7 +655,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 
	}



	if (n_tx) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB);

		reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;

		data = 0;
@@ -719,6 +719,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 
	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;

	reg |= (op->addr.nbytes - 1);

	writel(reg, reg_base + CQSPI_REG_SIZE);

	readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */

	return 0;

}
@@ -764,6 +765,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 
	reinit_completion(&cqspi->transfer_complete);

	writel(CQSPI_REG_INDIRECTRD_START_MASK,

	       reg_base + CQSPI_REG_INDIRECTRD);

	readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */



	while (remaining > 0) {

		if (use_irq &&
@@ -1062,6 +1064,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 
	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;

	reg |= (op->addr.nbytes - 1);

	writel(reg, reg_base + CQSPI_REG_SIZE);

	readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */

	return 0;

}
@@ -1090,6 +1093,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 
	reinit_completion(&cqspi->transfer_complete);

	writel(CQSPI_REG_INDIRECTWR_START_MASK,

	       reg_base + CQSPI_REG_INDIRECTWR);

	readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */



	/*

	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access

	 * Controller programming sequence, couple of cycles of
@@ -1186,7 +1191,7 @@ static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 
		 * CS2 to 4b'1011

		 * CS3 to 4b'0111

		 */

		chip_select = 0xF & ~(1 << chip_select);

		chip_select = 0xF & ~BIT(chip_select);

	}



	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
@@ -1272,9 +1277,9 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, 
	reg = readl(reg_base + CQSPI_REG_READCAPTURE);



	if (bypass)

		reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);

		reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);

	else

		reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);

		reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);



	reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK

		 << CQSPI_REG_READCAPTURE_DELAY_LSB);
@@ -1717,12 +1722,10 @@ static const struct spi_controller_mem_caps cqspi_mem_caps = { 


static int cqspi_setup_flash(struct cqspi_st *cqspi)

{

	unsigned int max_cs = cqspi->num_chipselect - 1;

	struct platform_device *pdev = cqspi->pdev;

	struct device *dev = &pdev->dev;

	struct cqspi_flash_pdata *f_pdata;

	unsigned int cs;

	int ret;

	int ret, cs, max_cs = -1;



	/* Get flash device data */

	for_each_available_child_of_node_scoped(dev->of_node, np) {
@@ -1735,10 +1738,10 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) 
		if (cs >= cqspi->num_chipselect) {

			dev_err(dev, "Chip select %d out of range.\n", cs);

			return -EINVAL;

		} else if (cs < max_cs) {

			max_cs = cs;

		}



		max_cs = max_t(int, cs, max_cs);



		f_pdata = &cqspi->f_pdata[cs];

		f_pdata->cqspi = cqspi;

		f_pdata->cs = cs;
@@ -1748,6 +1751,11 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) 
			return ret;

	}



	if (max_cs < 0) {

		dev_err(dev, "No flash device declared\n");

		return -ENODEV;

	}



	cqspi->num_chipselect = max_cs + 1;

	return 0;

}