Commit aca69900 authored by Michael Ellerman's avatar Michael Ellerman Committed by Andrew Morton
Browse files

powerpc/64e: drop MMU_FTR_TYPE_FSL_E checks in 64-bit code 

All 64-bit Book3E have MMU_FTR_TYPE_FSL_E, since A2 was removed, so remove
checks for it in 64-bit only code.

Link: https://lkml.kernel.org/r/2b0b0bc9752e6cece222e4e2050358da70bb631d.1719928057.git.christophe.leroy@csgroup.eu


Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Oscar Salvador <osalvador@suse.de>
Cc: Peter Xu <peterx@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent ceb9314f

arch/powerpc/kernel/setup_64.c

+1 −5
Original line number Diff line number Diff line
@@ -696,11 +696,7 @@ __init u64 ppc64_bolted_size(void) 
{

#ifdef CONFIG_PPC_BOOK3E_64

	/* Freescale BookE bolts the entire linear mapping */

	/* XXX: BookE ppc64_rma_limit setup seems to disagree? */

	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))

	return linear_map_top;

	/* Other BookE, we assume the first GB is bolted */

	return 1ul << 30;

#else

	/* BookS radix, does not take faults on linear mapping */

	if (early_radix_enabled())

arch/powerpc/mm/nohash/tlb_64e.c

+37 −60
Original line number Diff line number Diff line
@@ -86,9 +86,8 @@ static void __init setup_page_sizes(void) 
	int psize;



	unsigned int mmucfg = mfspr(SPRN_MMUCFG);

	int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);



	if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {

	if ((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {

		unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);

		unsigned int min_pg, max_pg;
@@ -115,7 +114,7 @@ static void __init setup_page_sizes(void) 
		goto out;

	}



	if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {

	if ((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {

		u32 tlb1cfg, tlb1ps;



		tlb0cfg = mfspr(SPRN_TLB0CFG);
@@ -213,7 +212,6 @@ static void early_init_this_mmu(void) 
	}

	mtspr(SPRN_MAS4, mas4);



	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

	unsigned int num_cams;

	bool map = true;
@@ -232,7 +230,6 @@ static void early_init_this_mmu(void) 
	if (map)

		linear_map_top = map_mem_in_cams(linear_map_top,

						 num_cams, false, true);

	}



	/* A sync won't hurt us after mucking around with

	 * the MMU configuration
@@ -242,16 +239,10 @@ static void early_init_this_mmu(void) 


static void __init early_init_mmu_global(void)

{

	/* XXX This should be decided at runtime based on supported

	 * page sizes in the TLB, but for now let's assume 16M is

	 * always there and a good fit (which it probably is)

	 *

	/*

	 * Freescale booke only supports 4K pages in TLB0, so use that.

	 */

	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))

	mmu_vmemmap_psize = MMU_PAGE_4K;

	else

		mmu_vmemmap_psize = MMU_PAGE_16M;



	/* XXX This code only checks for TLB 0 capabilities and doesn't

	 *     check what page size combos are supported by the HW. It
@@ -264,13 +255,10 @@ static void __init early_init_mmu_global(void) 
	/* Look for HW tablewalk support */

	setup_mmu_htw();



	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

	if (book3e_htw_mode == PPC_HTW_NONE) {

		extlb_level_exc = EX_TLB_SIZE;

		patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);

			patch_exception(0x1e0,

				exc_instruction_tlb_miss_bolted_book3e);

		}

		patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);

	}



	/* Set the global containing the top of the linear mapping
@@ -283,7 +271,6 @@ static void __init early_init_mmu_global(void) 


static void __init early_mmu_set_memory_limit(void)

{

	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

	/*

	 * Limit memory so we dont have linear faults.

	 * Unlike memblock_set_current_limit, which limits
@@ -292,7 +279,6 @@ static void __init early_mmu_set_memory_limit(void) 
	 * do this because highmem is not supported on 64-bit.

	 */

	memblock_enforce_memory_limit(linear_map_top);

	}



	memblock_set_current_limit(linear_map_top);

}
@@ -313,12 +299,8 @@ void early_init_mmu_secondary(void) 
void setup_initial_memory_limit(phys_addr_t first_memblock_base,

				phys_addr_t first_memblock_size)

{

	/* On non-FSL Embedded 64-bit, we adjust the RMA size to match

	 * the bolted TLB entry. We know for now that only 1G

	 * entries are supported though that may eventually

	 * change.

	 *

	 * on FSL Embedded 64-bit, usually all RAM is bolted, but with

	/*

	 * On FSL Embedded 64-bit, usually all RAM is bolted, but with

	 * unusual memory sizes it's possible for some RAM to not be mapped

	 * (such RAM is not used at all by Linux, since we don't support

	 * highmem on 64-bit).  We limit ppc64_rma_size to what would be
@@ -330,19 +312,14 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base, 
	 * We crop it to the size of the first MEMBLOCK to

	 * avoid going over total available memory just in case...

	 */

	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

	unsigned long linear_sz;

	unsigned int num_cams;



	/* use a quarter of the TLBCAM for bolted linear map */

	num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;



		linear_sz = map_mem_in_cams(first_memblock_size, num_cams,

					    true, true);



	linear_sz = map_mem_in_cams(first_memblock_size, num_cams, true, true);

	ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);

	} else

		ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);



	/* Finally limit subsequent allocations */

	memblock_set_current_limit(first_memblock_base + ppc64_rma_size);