Commit ad24f6e1 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Yury Norov
Browse files

drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro 



The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

Replace this driver's HIWORD_UPDATE with the FIELD_PREP_WM16 macro from
hw_bitfield.h. While at it, disambiguate the GRF write to SOC_CON7 by
splitting the definition into the individual bitflags. This is done
because FIELD_PREP_WM16 shifts the value for us according to the mask,
so writing the mask to itself to enable two bits is no longer something
that can be done. It should also not be done anyway because it hides the
true meaning of those two individual bit flags.

HDMI output with this patch has been tested on both RK3588 and RK3576.
On the former, with both present HDMI connectors.

Reviewed-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarYury Norov (NVIDIA) <yury.norov@gmail.com>
parent d6de45fd

drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c

+33 −35
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 


#include <linux/clk.h>

#include <linux/gpio/consumer.h>

#include <linux/hw_bitfield.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/platform_device.h>
@@ -66,7 +67,8 @@ 
#define RK3588_HDMI1_HPD_INT_MSK	BIT(15)

#define RK3588_HDMI1_HPD_INT_CLR	BIT(14)

#define RK3588_GRF_SOC_CON7		0x031c

#define RK3588_SET_HPD_PATH_MASK	GENMASK(13, 12)

#define RK3588_HPD_HDMI0_IO_EN_MASK	BIT(12)

#define RK3588_HPD_HDMI1_IO_EN_MASK	BIT(13)

#define RK3588_GRF_SOC_STATUS1		0x0384

#define RK3588_HDMI0_LEVEL_INT		BIT(16)

#define RK3588_HDMI1_LEVEL_INT		BIT(24)
@@ -80,7 +82,6 @@ 
#define RK3588_HDMI0_GRANT_SEL		BIT(10)

#define RK3588_HDMI1_GRANT_SEL		BIT(12)



#define HIWORD_UPDATE(val, mask)	((val) | (mask) << 16)

#define HOTPLUG_DEBOUNCE_MS		150

#define MAX_HDMI_PORT_NUM		2
@@ -185,11 +186,11 @@ static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) 
	u32 val;



	if (hdmi->port_id)

		val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,

				    RK3588_HDMI1_HPD_INT_CLR | RK3588_HDMI1_HPD_INT_MSK);

		val = (FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1) |

		       FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0));

	else

		val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,

				    RK3588_HDMI0_HPD_INT_CLR | RK3588_HDMI0_HPD_INT_MSK);

		val = (FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1) |

		       FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0));



	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);

}
@@ -218,8 +219,8 @@ static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) 
	struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;

	u32 val;



	val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR,

			    RK3576_HDMI_HPD_INT_CLR | RK3576_HDMI_HPD_INT_MSK);

	val = (FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) |

	       FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0));



	regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);

	regmap_write(hdmi->regmap, 0xa404, 0xffff0102);
@@ -254,7 +255,7 @@ static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) 


	regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat);

	if (intr_stat) {

		val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_MSK, RK3576_HDMI_HPD_INT_MSK);

		val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1);



		regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);

		return IRQ_WAKE_THREAD;
@@ -273,12 +274,12 @@ static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) 
	if (!intr_stat)

		return IRQ_NONE;



	val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR, RK3576_HDMI_HPD_INT_CLR);

	val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1);

	regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);

	mod_delayed_work(system_wq, &hdmi->hpd_work,

			 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));



	val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);

	val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);

	regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);



	return IRQ_HANDLED;
@@ -293,11 +294,9 @@ static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) 


	if (intr_stat) {

		if (hdmi->port_id)

			val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK,

					    RK3588_HDMI1_HPD_INT_MSK);

			val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);

		else

			val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,

					    RK3588_HDMI0_HPD_INT_MSK);

			val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);

		regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);

		return IRQ_WAKE_THREAD;

	}
@@ -315,20 +314,18 @@ static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) 
		return IRQ_NONE;



	if (hdmi->port_id)

		val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,

				    RK3588_HDMI1_HPD_INT_CLR);

		val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1);

	else

		val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,

				    RK3588_HDMI0_HPD_INT_CLR);

		val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1);

	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);



	mod_delayed_work(system_wq, &hdmi->hpd_work,

			 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));



	if (hdmi->port_id)

		val |= HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK);

		val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0);

	else

		val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);

		val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0);

	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);



	return IRQ_HANDLED;
@@ -338,14 +335,14 @@ static void dw_hdmi_qp_rk3576_io_init(struct rockchip_hdmi_qp *hdmi) 
{

	u32 val;



	val = HIWORD_UPDATE(RK3576_SCLIN_MASK, RK3576_SCLIN_MASK) |

	      HIWORD_UPDATE(RK3576_SDAIN_MASK, RK3576_SDAIN_MASK) |

	      HIWORD_UPDATE(RK3576_HDMI_GRANT_SEL, RK3576_HDMI_GRANT_SEL) |

	      HIWORD_UPDATE(RK3576_I2S_SEL_MASK, RK3576_I2S_SEL_MASK);

	val = FIELD_PREP_WM16(RK3576_SCLIN_MASK, 1) |

	      FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) |

	      FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) |

	      FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1);



	regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON14, val);



	val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);

	val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);

	regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);

}
@@ -353,27 +350,28 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) 
{

	u32 val;



	val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |

	      HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |

	      HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |

	      HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);

	val = FIELD_PREP_WM16(RK3588_SCLIN_MASK, 1) |

	      FIELD_PREP_WM16(RK3588_SDAIN_MASK, 1) |

	      FIELD_PREP_WM16(RK3588_MODE_MASK, 1) |

	      FIELD_PREP_WM16(RK3588_I2S_SEL_MASK, 1);

	regmap_write(hdmi->vo_regmap,

		     hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3,

		     val);



	val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, RK3588_SET_HPD_PATH_MASK);

	val = FIELD_PREP_WM16(RK3588_HPD_HDMI0_IO_EN_MASK, 1) |

	      FIELD_PREP_WM16(RK3588_HPD_HDMI1_IO_EN_MASK, 1);

	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);



	if (hdmi->port_id)

		val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, RK3588_HDMI1_GRANT_SEL);

		val = FIELD_PREP_WM16(RK3588_HDMI1_GRANT_SEL, 1);

	else

		val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, RK3588_HDMI0_GRANT_SEL);

		val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1);

	regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);



	if (hdmi->port_id)

		val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK);

		val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);

	else

		val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);

		val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);

	regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);

}