Commit d6de45fd authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Yury Norov
Browse files

phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro 



The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

phy-rockchip-samsung-dcphy is actually an exemplary example, where the
similarities to FIELD_PREP were spotted and the driver local macro has
the same semantics as the new FIELD_PREP_WM16 hw_bitfield.h macro.

Still, get rid of FIELD_PREP_HIWORD now that a shared implementation
exists, replacing the two instances of it with FIELD_PREP_WM16. This
gives us slightly better error checking; the value is now checked to fit
in 16 bits.

Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarYury Norov (NVIDIA) <yury.norov@gmail.com>
parent 9040ecd0

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

+3 −8
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/phy/phy.h>

#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/hw_bitfield.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>
@@ -20,12 +21,6 @@ 
#include <linux/regmap.h>

#include <linux/reset.h>



#define FIELD_PREP_HIWORD(_mask, _val)		\

	(					\

		FIELD_PREP((_mask), (_val)) |	\

		((_mask) << 16)			\

	)



#define BIAS_CON0		0x0000

#define I_RES_CNTL_MASK		GENMASK(6, 4)

#define I_RES_CNTL(x)		FIELD_PREP(I_RES_CNTL_MASK, x)
@@ -252,8 +247,8 @@ 


/* MIPI_CDPHY_GRF registers */

#define MIPI_DCPHY_GRF_CON0		0x0000

#define S_CPHY_MODE			FIELD_PREP_HIWORD(BIT(3), 1)

#define M_CPHY_MODE			FIELD_PREP_HIWORD(BIT(0), 1)

#define S_CPHY_MODE			FIELD_PREP_WM16(BIT(3), 1)

#define M_CPHY_MODE			FIELD_PREP_WM16(BIT(0), 1)



enum hs_drv_res_ohm {

	STRENGTH_30_OHM = 0x8,