Commit b2177850 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.16-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Fix Amlogic G12 SPICC clock sources
 - Compile test Amlogic clocks only if ARCH_MESON is set

* tag 'clk-meson-v6.16-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc
parents 0af2f6be 0afce85e

drivers/clk/meson/Kconfig

+8 −8
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ config COMMON_CLK_MESON_CPU_DYNDIV 
config COMMON_CLK_MESON8B

	bool "Meson8 SoC Clock controller support"

	depends on ARM

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_MPLL
@@ -70,7 +70,7 @@ config COMMON_CLK_MESON8B 
config COMMON_CLK_GXBB

	tristate "GXBB and GXL SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_VID_PLL_DIV
@@ -86,7 +86,7 @@ config COMMON_CLK_GXBB 
config COMMON_CLK_AXG

	tristate "AXG SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_MPLL
@@ -136,7 +136,7 @@ config COMMON_CLK_A1_PERIPHERALS 
config COMMON_CLK_C3_PLL

	tristate "Amlogic C3 PLL clock controller"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_PLL

	select COMMON_CLK_MESON_CLKC_UTILS
@@ -149,7 +149,7 @@ config COMMON_CLK_C3_PLL 
config COMMON_CLK_C3_PERIPHERALS

	tristate "Amlogic C3 peripherals clock controller"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_CLKC_UTILS
@@ -163,7 +163,7 @@ config COMMON_CLK_C3_PERIPHERALS 
config COMMON_CLK_G12A

	tristate "G12 and SM1 SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_MPLL
@@ -181,7 +181,7 @@ config COMMON_CLK_G12A 
config COMMON_CLK_S4_PLL

	tristate "S4 SoC PLL clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PLL
@@ -194,7 +194,7 @@ config COMMON_CLK_S4_PLL 
config COMMON_CLK_S4_PERIPHERALS

	tristate "S4 SoC peripherals clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

drivers/clk/meson/g12a.c

+1 −0
Original line number Diff line number Diff line
@@ -4093,6 +4093,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { 
	{ .hw = &g12a_clk81.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div2.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};