Commit b3970e97 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-7.1-2026-03-19' of https://gitlab.freedesktop.org/agd5f/linux into drm-next



amd-drm-next-7.1-2026-03-19:

amdgpu:
- Fix gamma 2.2 colorop TFs
- BO list fix
- LTO fix
- DC FP fix
- DisplayID handling fix
- DCN 2.01 fix
- MMHUB boundary fixes
- ISP fix
- TLB fence fix
- Hainan pm fix
- UserQ fixes
- MES 12.1 Updates
- GC 12.1 updates
- RAS fixes
- DML updates
- Cursor fixes
- SWSMU cleanups
- Misc cleanups
- Clean up duplicate format modifiers
- Devcoredump updates
- Cleanup mmhub cid handling
- Initial VCN 5.0.2 support
- Initial JPEG 5.0.2 support
- PSP 13.0.15 updates

amdkfd:
- Queue properties fix
- GC 12.1 updates

radeon:
- Hainan pm fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260319173334.479766-1-alexander.deucher@amd.com
parents d93f8ea0 daf9f9dd
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+2 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ amdgpu-y += \
	vcn_v4_0_5.o \
	vcn_v5_0_0.o \
	vcn_v5_0_1.o \
	vcn_v5_0_2.o \
	amdgpu_jpeg.o \
	jpeg_v1_0.o \
	jpeg_v2_0.o \
@@ -223,6 +224,7 @@ amdgpu-y += \
	jpeg_v4_0_5.o \
	jpeg_v5_0_0.o \
	jpeg_v5_0_1.o \
	jpeg_v5_0_2.o \
	jpeg_v5_3_0.o

# add VPE block
+6 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ struct kfd_vm_fault_info;
struct amdgpu_hive_info;
struct amdgpu_reset_context;
struct amdgpu_reset_control;
struct amdgpu_coredump_info;

enum amdgpu_cp_irq {
	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
@@ -1147,6 +1148,11 @@ struct amdgpu_device {

	struct amdgpu_reset_domain	*reset_domain;

#ifdef CONFIG_DEV_COREDUMP
	struct amdgpu_coredump_info	*coredump;
	struct work_struct		coredump_work;
#endif

	struct mutex			benchmark_mutex;

	bool                            scpm_enabled;
+1 −1
Original line number Diff line number Diff line
@@ -330,7 +330,7 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev,

	watch_address_cntl = 0;
	watch_address_low = lower_32_bits(watch_address);
	watch_address_high = upper_32_bits(watch_address) & 0xffff;
	watch_address_high = upper_32_bits(watch_address) & 0x1ffffff;

	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
			TCP_WATCH0_CNTL,
+4 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@

#define AMDGPU_BO_LIST_MAX_PRIORITY	32u
#define AMDGPU_BO_LIST_NUM_BUCKETS	(AMDGPU_BO_LIST_MAX_PRIORITY + 1)
#define AMDGPU_BO_LIST_MAX_ENTRIES	(128 * 1024)

static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu)
{
@@ -188,6 +189,9 @@ int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
	const uint32_t bo_number = in->bo_number;
	struct drm_amdgpu_bo_list_entry *info;

	if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES)
		return -EINVAL;

	/* copy the handle array from userspace to a kernel buffer */
	if (likely(info_size == bo_info_size)) {
		info = vmemdup_array_user(uptr, bo_number, info_size);
+2 −0
Original line number Diff line number Diff line
@@ -1231,6 +1231,8 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector
		case CONNECTOR_OBJECT_ID_HDMI_TYPE_B:
			max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2;
			break;
		default:
			return MODE_BAD;
		}

		/* When the display EDID claims that it's an HDMI display,
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