Commit b4bb3aaf authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c 



Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4d942ae3

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+0 −23
Original line number Diff line number Diff line
@@ -540,29 +540,6 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 
	return ret;

}



int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)

{

	struct smu_feature *feature = &smu->smu_feature;

	int feature_id;

	int ret = 0;



	if (smu->is_apu)

		return 1;

	feature_id = smu_cmn_to_asic_specific_index(smu,

						    CMN2ASIC_MAPPING_FEATURE,

						    mask);

	if (feature_id < 0)

		return 0;



	WARN_ON(feature_id > feature->feature_num);



	mutex_lock(&feature->mutex);

	ret = test_bit(feature_id, feature->enabled);

	mutex_unlock(&feature->mutex);



	return ret;

}



int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,

			    bool enable)

{

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+15 −14
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) 


	/* socclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.soc_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_SOCCLK,

						     dpm_table);
@@ -298,7 +298,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) 


	/* gfxclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.gfx_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_GFXCLK,

						     dpm_table);
@@ -316,7 +316,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) 


	/* memclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.uclk_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_UCLK,

						     dpm_table);
@@ -334,7 +334,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) 


	/* fclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.fclk_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_FCLK,

						     dpm_table);
@@ -650,31 +650,31 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu, 
		 * We can use Average_* for dpm disabled case.

		 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.

		 */

		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))

			member_type = METRICS_CURR_GFXCLK;

		else

			member_type = METRICS_AVERAGE_GFXCLK;

		break;

	case PPCLK_UCLK:

		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))

			member_type = METRICS_CURR_UCLK;

		else

			member_type = METRICS_AVERAGE_UCLK;

		break;

	case PPCLK_SOCCLK:

		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))

			member_type = METRICS_CURR_SOCCLK;

		else

			member_type = METRICS_AVERAGE_SOCCLK;

		break;

	case PPCLK_VCLK:

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))

			member_type = METRICS_CURR_VCLK;

		else

			member_type = METRICS_AVERAGE_VCLK;

		break;

	case PPCLK_DCLK:

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))

			member_type = METRICS_CURR_DCLK;

		else

			member_type = METRICS_AVERAGE_DCLK;
@@ -820,7 +820,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, 
	uint32_t freq;

	int ret = 0;



	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&

	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {

		freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;

		ret = smu_send_smc_msg_with_param(smu,
@@ -834,7 +834,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, 
		}

	}



	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&

	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {

		freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;

		ret = smu_send_smc_msg_with_param(smu,
@@ -848,7 +848,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, 
		}

	}



	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&

	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {

		freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;

		ret = smu_send_smc_msg_with_param(smu,
@@ -1837,7 +1837,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 
	int ret = 0;



	if (enable) {

		if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);

			if (ret) {

				dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
@@ -1846,7 +1846,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 
		}

		power_gate->vcn_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);

			if (ret) {

				dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
@@ -2285,6 +2285,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { 
	.init_display_count = NULL,

	.set_allowed_mask = smu_v11_0_set_allowed_mask,

	.get_enabled_mask = smu_v11_0_get_enabled_mask,

	.feature_is_enabled = smu_cmn_feature_is_enabled,

	.notify_display_change = NULL,

	.set_power_limit = smu_v11_0_set_power_limit,

	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+1 −2
Original line number Diff line number Diff line
@@ -533,6 +533,7 @@ struct pptable_funcs { 
	int (*init_display_count)(struct smu_context *smu, uint32_t count);

	int (*set_allowed_mask)(struct smu_context *smu);

	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);

	int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);

	int (*notify_display_change)(struct smu_context *smu);

	int (*set_power_limit)(struct smu_context *smu, uint32_t n);

	int (*init_max_sustainable_clocks)(struct smu_context *smu);
@@ -728,8 +729,6 @@ extern const struct amd_ip_funcs smu_ip_funcs; 
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;

extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;



extern int smu_feature_is_enabled(struct smu_context *smu,

				  enum smu_feature_mask mask);

extern int smu_feature_set_enabled(struct smu_context *smu,

				   enum smu_feature_mask mask, bool enable);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+16 −15
Original line number Diff line number Diff line
@@ -601,7 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* socclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.soc_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_SOCCLK,

						     dpm_table);
@@ -619,7 +619,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* gfxclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.gfx_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_GFXCLK,

						     dpm_table);
@@ -637,7 +637,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* uclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.uclk_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_UCLK,

						     dpm_table);
@@ -655,7 +655,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* vclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.vclk_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_VCLK,

						     dpm_table);
@@ -673,7 +673,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* dclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.dclk_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DCLK,

						     dpm_table);
@@ -691,7 +691,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* dcefclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.dcef_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DCEFCLK,

						     dpm_table);
@@ -709,7 +709,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* pixelclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.pixel_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_PIXCLK,

						     dpm_table);
@@ -727,7 +727,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* displayclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.display_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DISPCLK,

						     dpm_table);
@@ -745,7 +745,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 


	/* phyclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.phy_table;

	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_PHYCLK,

						     dpm_table);
@@ -772,14 +772,14 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 


	if (enable) {

		/* vcn dpm on is a prerequisite for vcn power gate messages */

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);

			if (ret)

				return ret;

		}

		power_gate->vcn_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);

			if (ret)

				return ret;
@@ -797,14 +797,14 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 
	int ret = 0;



	if (enable) {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

			ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);

			if (ret)

				return ret;

		}

		power_gate->jpeg_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);

			if (ret)

				return ret;
@@ -1249,7 +1249,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu) 
	if (ret)

		return ret;



	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);

		if (ret)

			return ret;
@@ -1565,7 +1565,7 @@ static int navi10_notify_smc_display_config(struct smu_context *smu) 
		}

	}



	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

		if (ret) {

			dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
@@ -2300,6 +2300,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.init_display_count = smu_v11_0_init_display_count,

	.set_allowed_mask = smu_v11_0_set_allowed_mask,

	.get_enabled_mask = smu_v11_0_get_enabled_mask,

	.feature_is_enabled = smu_cmn_feature_is_enabled,

	.notify_display_change = smu_v11_0_notify_display_change,

	.set_power_limit = smu_v11_0_set_power_limit,

	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

drivers/gpu/drm/amd/powerplay/renoir_ppt.c

+6 −5
Original line number Diff line number Diff line
@@ -463,14 +463,14 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 


	if (enable) {

		/* vcn dpm on is a prerequisite for vcn power gate messages */

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);

			if (ret)

				return ret;

		}

		power_gate->vcn_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);

			if (ret)

				return ret;
@@ -488,14 +488,14 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 
	int ret = 0;



	if (enable) {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);

			if (ret)

				return ret;

		}

		power_gate->jpeg_gated = false;

	} else {

		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {

			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);

			if (ret)

				return ret;
@@ -571,7 +571,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) { 
	};



	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {

		if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))

		if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))

		    continue;



		clk_type = clk_feature_map[i].clk_type;
@@ -1019,6 +1019,7 @@ static const struct pptable_funcs renoir_ppt_funcs = { 
	.fini_smc_tables = smu_v12_0_fini_smc_tables,

	.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,

	.get_enabled_mask = smu_v12_0_get_enabled_mask,

	.feature_is_enabled = smu_cmn_feature_is_enabled,

	.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,

	.mode2_reset = smu_v12_0_mode2_reset,

	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,