Commit b5bad77e authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/registers: Sync GPU registers from mesa 



In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.

Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU
register xml").

Cc: Karmjit Mahil <karmjit.mahil@igalia.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673558/
parent 60e9f776

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+4 −4
Original line number Diff line number Diff line
@@ -264,8 +264,8 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 
	 * Needed for preemption

	 */

	OUT_PKT7(ring, CP_MEM_WRITE, 5);

	OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));

	OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));

	OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_LO(lower_32_bits(memptr)));

	OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_HI(upper_32_bits(memptr)));

	OUT_RING(ring, lower_32_bits(ttbr));

	OUT_RING(ring, upper_32_bits(ttbr));

	OUT_RING(ring, ctx->seqno);
@@ -295,9 +295,9 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 
		 */

		OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);

		OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));

		OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(

		OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(

				REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));

		OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));

		OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0));

		OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));

		OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));

		OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

+2 −2
Original line number Diff line number Diff line
@@ -111,9 +111,9 @@ static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu) 


	postamble[count++] = PKT7(CP_WAIT_REG_MEM, 6);

	postamble[count++] = CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ);

	postamble[count++] = CP_WAIT_REG_MEM_1_POLL_ADDR_LO(

	postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_LO(

				REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS);

	postamble[count++] = CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0);

	postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_HI(0);

	postamble[count++] = CP_WAIT_REG_MEM_3_REF(0x1);

	postamble[count++] = CP_WAIT_REG_MEM_4_MASK(0x1);

	postamble[count++] = CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0);

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

+406 −296

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml

+0 −40
Original line number Diff line number Diff line
@@ -9,38 +9,6 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 


<domain name="A6XX_TEX_SAMP" width="32">

	<doc>Texture sampler dwords</doc>

	<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->

		<value name="A6XX_TEX_NEAREST" value="0"/>

		<value name="A6XX_TEX_LINEAR" value="1"/>

		<value name="A6XX_TEX_ANISO" value="2"/>

		<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->

	</enum>

	<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->

		<value name="A6XX_TEX_REPEAT" value="0"/>

		<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>

		<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>

		<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>

		<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>

	</enum>

	<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->

		<value name="A6XX_TEX_ANISO_1" value="0"/>

		<value name="A6XX_TEX_ANISO_2" value="1"/>

		<value name="A6XX_TEX_ANISO_4" value="2"/>

		<value name="A6XX_TEX_ANISO_8" value="3"/>

		<value name="A6XX_TEX_ANISO_16" value="4"/>

	</enum>

	<enum name="a6xx_reduction_mode">

		<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>

		<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>

		<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>

	</enum>

	<enum name="a6xx_fast_border_color">

		<!--                           R B G A -->

		<value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/>

		<value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/>

		<value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/>

		<value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/>

	</enum>



	<reg32 offset="0" name="0">

		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
@@ -79,14 +47,6 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 


<domain name="A6XX_TEX_CONST" width="32" varset="chip">

	<doc>Texture constant dwords</doc>

	<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->

		<value name="A6XX_TEX_X" value="0"/>

		<value name="A6XX_TEX_Y" value="1"/>

		<value name="A6XX_TEX_Z" value="2"/>

		<value name="A6XX_TEX_W" value="3"/>

		<value name="A6XX_TEX_ZERO" value="4"/>

		<value name="A6XX_TEX_ONE" value="5"/>

	</enum>

	<reg32 offset="0" name="0">

		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>

		<bitfield name="SRGB" pos="2" type="boolean"/>

drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml

+48 −2
Original line number Diff line number Diff line
@@ -320,14 +320,14 @@ to upconvert to 32b float internally? 
16b float:   3

 -->

<enum name="a6xx_2d_ifmt">

	<value value="0x10" name="R2D_UNORM8"/>

	<value value="0x7"  name="R2D_INT32"/>

	<value value="0x6"  name="R2D_INT16"/>

	<value value="0x5"  name="R2D_INT8"/>

	<value value="0x4"  name="R2D_FLOAT32"/>

	<value value="0x3"  name="R2D_FLOAT16"/>

	<value value="0x2"  name="R2D_SNORM8"/>

	<value value="0x1"  name="R2D_UNORM8_SRGB"/>

	<value value="0x0"  name="R2D_RAW"/>

	<value value="0x0"  name="R2D_UNORM8"/>

</enum>



<enum name="a6xx_tex_type">
@@ -380,4 +380,50 @@ to upconvert to 32b float internally? 
	<value value="0x3" name="TESS_CCW_TRIS"/>

</enum>



<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->

	<value name="A6XX_TEX_NEAREST" value="0"/>

	<value name="A6XX_TEX_LINEAR" value="1"/>

	<value name="A6XX_TEX_ANISO" value="2"/>

	<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->

</enum>



<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->

	<value name="A6XX_TEX_REPEAT" value="0"/>

	<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>

	<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>

	<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>

	<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>

</enum>



<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->

	<value name="A6XX_TEX_ANISO_1" value="0"/>

	<value name="A6XX_TEX_ANISO_2" value="1"/>

	<value name="A6XX_TEX_ANISO_4" value="2"/>

	<value name="A6XX_TEX_ANISO_8" value="3"/>

	<value name="A6XX_TEX_ANISO_16" value="4"/>

</enum>



<enum name="a6xx_reduction_mode">

	<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>

	<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>

	<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>

</enum>



<enum name="a6xx_fast_border_color">

	<!--                           R B G A -->

	<value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/>

	<value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/>

	<value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/>

	<value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/>

</enum>



<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->

	<value name="A6XX_TEX_X" value="0"/>

	<value name="A6XX_TEX_Y" value="1"/>

	<value name="A6XX_TEX_Z" value="2"/>

	<value name="A6XX_TEX_W" value="3"/>

	<value name="A6XX_TEX_ZERO" value="4"/>

	<value name="A6XX_TEX_ONE" value="5"/>

</enum>



</database>