Commit b61821bb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-fixes-2024-05-10' of... 

Merge tag 'drm-misc-fixes-2024-05-10' of https://gitlab.freedesktop.org/drm/misc/kernel

 into drm-fixes

Short summary of fixes pull:

core:
- fix connector debugging output

meson:
- dw-hdmi: power-up fixes
- dw-hdmi: add badngap setting for g12

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510072027.GA9131@linux.fritz.box
parents 06fbf84f 6897204e

drivers/gpu/drm/drm_connector.c

+1 −1
Original line number Diff line number Diff line
@@ -2940,7 +2940,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, 
						     dev->mode_config.max_width,

						     dev->mode_config.max_height);

		else

			drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe",

			drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe\n",

				    connector->base.id, connector->name);

	}

drivers/gpu/drm/meson/meson_dw_hdmi.c

+31 −39
Original line number Diff line number Diff line
@@ -106,6 +106,8 @@ 
#define HHI_HDMI_CLK_CNTL	0x1cc /* 0x73 */

#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 */

#define HHI_HDMI_PHY_CNTL1	0x3a4 /* 0xe9 */

#define  PHY_CNTL1_INIT		0x03900000

#define  PHY_INVERT		BIT(17)

#define HHI_HDMI_PHY_CNTL2	0x3a8 /* 0xea */

#define HHI_HDMI_PHY_CNTL3	0x3ac /* 0xeb */

#define HHI_HDMI_PHY_CNTL4	0x3b0 /* 0xec */
@@ -130,6 +132,8 @@ struct meson_dw_hdmi_data { 
				    unsigned int addr);

	void		(*dwc_write)(struct meson_dw_hdmi *dw_hdmi,

				     unsigned int addr, unsigned int data);

	u32 cntl0_init;

	u32 cntl1_init;

};



struct meson_dw_hdmi {
@@ -384,26 +388,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	    dw_hdmi_bus_fmt_is_420(hdmi))

		mode_is_420 = true;



	/* Enable clocks */

	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);



	/* Bring HDMITX MEM output of power down */

	regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);



	/* Bring out of reset */

	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET,  0);



	/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3, 0x3);



	/* Enable cec_clk and hdcp22_tmdsclk_en */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3 << 4, 0x3 << 4);



	/* Enable normal output to PHY */

	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));



	/* TMDS pattern setup */

	if (mode->clock > 340000 && !mode_is_420) {

		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
@@ -425,20 +409,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	/* Setup PHY parameters */

	meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);



	/* Setup PHY */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

			   0xffff << 16, 0x0390 << 16);



	/* BIT_INVERT */

	if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||

	    dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||

	    dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), 0);

	else

		regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,

				   BIT(17), BIT(17));



	/* Disable clock, fifo, fifo_wr */

	regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
@@ -492,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 


	DRM_DEBUG_DRIVER("\n");



	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);

	/* Fallback to init mode */

	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);

	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);

}



static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
@@ -610,11 +582,22 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = { 
	.fast_io = true,

};



static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {

static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {

	.top_read = dw_hdmi_top_read,

	.top_write = dw_hdmi_top_write,

	.dwc_read = dw_hdmi_dwc_read,

	.dwc_write = dw_hdmi_dwc_write,

	.cntl0_init = 0x0,

	.cntl1_init = PHY_CNTL1_INIT | PHY_INVERT,

};



static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {

	.top_read = dw_hdmi_top_read,

	.top_write = dw_hdmi_top_write,

	.dwc_read = dw_hdmi_dwc_read,

	.dwc_write = dw_hdmi_dwc_write,

	.cntl0_init = 0x0,

	.cntl1_init = PHY_CNTL1_INIT,

};



static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
@@ -622,6 +605,8 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = { 
	.top_write = dw_hdmi_g12a_top_write,

	.dwc_read = dw_hdmi_g12a_dwc_read,

	.dwc_write = dw_hdmi_g12a_dwc_write,

	.cntl0_init = 0x000b4242, /* Bandgap */

	.cntl1_init = PHY_CNTL1_INIT,

};



static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
@@ -656,6 +641,13 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) 
	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_CLK_CNTL, 0xff);



	/* Enable normal output to PHY */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));



	/* Setup PHY */

	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);

	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);



	/* Enable HDMI-TX Interrupt */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,

				       HDMITX_TOP_INTR_CORE);
@@ -865,11 +857,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = { 


static const struct of_device_id meson_dw_hdmi_of_table[] = {

	{ .compatible = "amlogic,meson-gxbb-dw-hdmi",

	  .data = &meson_dw_hdmi_gx_data },

	  .data = &meson_dw_hdmi_gxbb_data },

	{ .compatible = "amlogic,meson-gxl-dw-hdmi",

	  .data = &meson_dw_hdmi_gx_data },

	  .data = &meson_dw_hdmi_gxl_data },

	{ .compatible = "amlogic,meson-gxm-dw-hdmi",

	  .data = &meson_dw_hdmi_gx_data },

	  .data = &meson_dw_hdmi_gxl_data },

	{ .compatible = "amlogic,meson-g12a-dw-hdmi",

	  .data = &meson_dw_hdmi_g12a_data },

	{ }