Loading drivers/net/phy/phy-c45.c +31 −0 Original line number Diff line number Diff line Loading @@ -830,6 +830,30 @@ static int genphy_c45_read_eee_cap1(struct phy_device *phydev) return 0; } /** * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 * @phydev: target phy_device struct */ static int genphy_c45_read_eee_cap2(struct phy_device *phydev) { int val; /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 * (Register 3.21) */ val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); if (val < 0) return val; /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ if (val == 0xffff) return 0; mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); return 0; } /** * genphy_c45_read_eee_abilities - read supported EEE link modes * @phydev: target phy_device struct Loading @@ -848,6 +872,13 @@ int genphy_c45_read_eee_abilities(struct phy_device *phydev) return val; } /* Same for cap2 (3.21) */ if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { val = genphy_c45_read_eee_cap2(phydev); if (val) return val; } if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, phydev->supported)) { /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register Loading Loading
drivers/net/phy/phy-c45.c +31 −0 Original line number Diff line number Diff line Loading @@ -830,6 +830,30 @@ static int genphy_c45_read_eee_cap1(struct phy_device *phydev) return 0; } /** * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 * @phydev: target phy_device struct */ static int genphy_c45_read_eee_cap2(struct phy_device *phydev) { int val; /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 * (Register 3.21) */ val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); if (val < 0) return val; /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ if (val == 0xffff) return 0; mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); return 0; } /** * genphy_c45_read_eee_abilities - read supported EEE link modes * @phydev: target phy_device struct Loading @@ -848,6 +872,13 @@ int genphy_c45_read_eee_abilities(struct phy_device *phydev) return val; } /* Same for cap2 (3.21) */ if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { val = genphy_c45_read_eee_cap2(phydev); if (val) return val; } if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, phydev->supported)) { /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register Loading