Commit b7731065 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
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iommu/amd: Introduce per-device GCR3 table 



AMD IOMMU GCR3 table is indexed by PASID. Each entry stores guest CR3
register value, which is an address to the root of guest IO page table.
The GCR3 table can be programmed per-device. However, Linux AMD IOMMU
driver currently managing the table on a per-domain basis.

PASID is a device feature. When SVA is enabled it will bind PASID to
device, not domain. Hence it makes sense to have per device GCR3 table.

Introduce struct iommu_dev_data.gcr3_tbl_info to keep track of GCR3 table
configuration. This will eventually replaces gcr3 related variables in
protection_domain structure.

Suggested-by: default avatarJason Gunthorpe <jgg@ziepe.ca>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20240205115615.6053-6-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent fda5108e

drivers/iommu/amd/amd_iommu_types.h

+7 −0
Original line number Diff line number Diff line
@@ -533,6 +533,12 @@ struct amd_irte_ops; 
#define io_pgtable_cfg_to_data(x) \

	container_of((x), struct amd_io_pgtable, pgtbl_cfg)



struct gcr3_tbl_info {

	u64	*gcr3_tbl;	/* Guest CR3 table */

	int	glx;		/* Number of levels for GCR3 table */

	u32	pasid_cnt;	/* Track attached PASIDs */

};



struct amd_io_pgtable {

	struct io_pgtable_cfg	pgtbl_cfg;

	struct io_pgtable	iop;
@@ -814,6 +820,7 @@ struct iommu_dev_data { 
	struct list_head list;		  /* For domain->dev_list */

	struct llist_node dev_data_list;  /* For global dev_data_list */

	struct protection_domain *domain; /* Domain the device is bound to */

	struct gcr3_tbl_info gcr3_info;   /* Per-device GCR3 table */

	struct device *dev;

	u16 devid;			  /* PCI Device ID */