Commit b7f67545 authored by Marek Vasut's avatar Marek Vasut Committed by Abel Vesa
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clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x 



The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used
to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so
they can be generated by the PLL and used to produce e.g. 13 MHz or
26 MHz on CLKOUTn output.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20241112013805.333798-1-marex@denx.de


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent a9b7c84d

drivers/clk/imx/clk-pll14xx.c

+2 −0
Original line number Diff line number Diff line
@@ -56,7 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { 
	PLL_1416X_RATE(700000000U,  350, 3, 2),

	PLL_1416X_RATE(640000000U,  320, 3, 2),

	PLL_1416X_RATE(600000000U,  300, 3, 2),

	PLL_1416X_RATE(416000000U,  208, 3, 2),

	PLL_1416X_RATE(320000000U,  160, 3, 2),

	PLL_1416X_RATE(208000000U,  208, 3, 3),

};



static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {