Commit b9251e64 authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
Browse files

phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 



Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5
using the overlays setup (only supported Gear 5 before), and sync
back with the latest Qualcomm recommended values.

The new recommended values allow a solid 50% bump in sequential
read/write benchmarks on the SM8650 QRD & HDK reference boards.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 6f9d713f

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h

+4 −0
Original line number Diff line number Diff line
@@ -30,5 +30,9 @@ 
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1		0x1f4

#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1		0x1fc

#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME		0x220

#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4		0x240

#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5		0x244

#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6		0x248

#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7		0x24c



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

+6 −0
Original line number Diff line number Diff line
@@ -25,12 +25,15 @@ 
#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4			0xf0

#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS			0xf4

#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL			0x178

#define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4			0x1ac

#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x1bc

#define QSERDES_UFS_V6_RX_INTERFACE_MODE			0x1e0

#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3			0x1c4

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0			0x208

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1			0x20c

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2			0x210

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3			0x214

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4			0x218

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6			0x220

#define QSERDES_UFS_V6_RX_MODE_RATE2_B3				0x238

#define QSERDES_UFS_V6_RX_MODE_RATE2_B6				0x244
@@ -38,6 +41,9 @@ 
#define QSERDES_UFS_V6_RX_MODE_RATE3_B4				0x260

#define QSERDES_UFS_V6_RX_MODE_RATE3_B5				0x264

#define QSERDES_UFS_V6_RX_MODE_RATE3_B8				0x270

#define QSERDES_UFS_V6_RX_MODE_RATE4_B0				0x274

#define QSERDES_UFS_V6_RX_MODE_RATE4_B1				0x278

#define QSERDES_UFS_V6_RX_MODE_RATE4_B2				0x27c

#define QSERDES_UFS_V6_RX_MODE_RATE4_B3				0x280

#define QSERDES_UFS_V6_RX_MODE_RATE4_B4				0x284

#define QSERDES_UFS_V6_RX_MODE_RATE4_B6				0x28c

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+58 −15
Original line number Diff line number Diff line
@@ -862,17 +862,20 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
@@ -880,17 +883,28 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 
};



static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
@@ -898,23 +912,41 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 
	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),

};



struct qmp_ufs_offsets {
@@ -1475,6 +1507,17 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 
		.pcs		= sm8650_ufsphy_pcs,

		.pcs_num	= ARRAY_SIZE(sm8650_ufsphy_pcs),

	},

	.tbls_hs_overlay[0] = {

		.pcs		= sm8650_ufsphy_g4_pcs,

		.pcs_num	= ARRAY_SIZE(sm8650_ufsphy_g4_pcs),

		.max_gear	= UFS_HS_G4,

	},

	.tbls_hs_overlay[1] = {

		.pcs		= sm8650_ufsphy_g5_pcs,

		.pcs_num	= ARRAY_SIZE(sm8650_ufsphy_g5_pcs),

		.max_gear	= UFS_HS_G5,

	},



	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= ufsphy_v6_regs_layout,