Unverified Commit b9a603da authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "riscv: Separate vendor extensions from standard extensions" 

Charlie Jenkins <charlie@rivosinc.com> says:

All extensions, both standard and vendor, live in one struct
"riscv_isa_ext". There is currently one vendor extension, xandespmu, but
it is likely that more vendor extensions will be added to the kernel in
the future. As more vendor extensions (and standard extensions) are
added, riscv_isa_ext will become more bloated with a mix of vendor and
standard extensions.

This also allows each vendor to be conditionally enabled through
Kconfig.

* b4-shazam-merge:
  riscv: cpufeature: Extract common elements from extension checking
  riscv: Introduce vendor variants of extension helpers
  riscv: Add vendor extensions to /proc/cpuinfo
  riscv: Extend cpufeature.c to detect vendor extensions

Link: https://lore.kernel.org/r/20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 82b46168 d4c8d79f

arch/riscv/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -820,6 +820,8 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS 


endchoice



source "arch/riscv/Kconfig.vendor"



endmenu # "Platform type"



menu "Kernel features"

arch/riscv/Kconfig.vendor

0 → 100644
+19 −0
Original line number Diff line number Diff line 
menu "Vendor extensions"



config RISCV_ISA_VENDOR_EXT

	bool



menu "Andes"

config RISCV_ISA_VENDOR_EXT_ANDES

	bool "Andes vendor extension support"

	select RISCV_ISA_VENDOR_EXT

	default y

	help

	  Say N here if you want to disable all Andes vendor extension

	  support. This will cause any Andes vendor extensions that are

	  requested by hardware probing to be ignored.



	  If you don't know what to do here, say Y.

endmenu



endmenu

arch/riscv/errata/andes/errata.c

+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <asm/processor.h>

#include <asm/sbi.h>

#include <asm/vendorid_list.h>

#include <asm/vendor_extensions.h>



#define ANDES_AX45MP_MARCHID		0x8000000000008a45UL

#define ANDES_AX45MP_MIMPID		0x500UL
@@ -65,6 +66,8 @@ void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct al 
					      unsigned long archid, unsigned long impid,

					      unsigned int stage)

{

	BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);



	if (stage == RISCV_ALTERNATIVES_BOOT)

		errata_probe_iocp(stage, archid, impid);

arch/riscv/errata/sifive/errata.c

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <asm/alternative.h>

#include <asm/vendorid_list.h>

#include <asm/errata_list.h>

#include <asm/vendor_extensions.h>



struct errata_info_t {

	char name[32];
@@ -96,6 +97,8 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
	u32 cpu_apply_errata = 0;

	u32 tmp;



	BUILD_BUG_ON(ERRATA_SIFIVE_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return;

arch/riscv/errata/thead/errata.c

+3 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <asm/io.h>

#include <asm/patch.h>

#include <asm/vendorid_list.h>

#include <asm/vendor_extensions.h>



#define CSR_TH_SXSTATUS		0x5c0

#define SXSTATUS_MAEE		_AC(0x200000, UL)
@@ -166,6 +167,8 @@ void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
	u32 tmp;

	void *oldptr, *altptr;



	BUILD_BUG_ON(ERRATA_THEAD_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);



	for (alt = begin; alt < end; alt++) {

		if (alt->vendor_id != THEAD_VENDOR_ID)

			continue;