Commit ba65a4e7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull clk updates from Stephen Boyd:
 "This is entirely SoC clk drivers.

  The majority diff wise is for the new Rockchip and Qualcomm clk
  drivers which is mostly lines and lines of data structures to describe
  the clk hardware in these SoCs. Beyond those two, Renesas continues to
  incrementally add clks to their SoC drivers, causing them to show up
  higher in the diffstat this time because they added quite a few clks
  all over the place.

  Overall it is a semi-quiet release that has some new clk drivers and
  the usual fixes for clock data that was wrong or missing and
  non-critical cleanups that plug error paths or fix typos.

  New Drivers:
   - Qualcomm IPQ5424 Network Subsystem Clock Controller
   - Qualcomm SM8750 Video Clock Controller
   - Rockchip RV1126B and RK3506 clock drivers
   - i.MX8ULP SIM LPAV clock driver
   - Samsung ACPM (firmware interface) clock driver
   - Altera Agilex5 clock driver"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (117 commits)
  clk: keystone: fix compile testing
  clk: keystone: syscon-clk: fix regmap leak on probe failure
  clk: qcom: Mark camcc_sm7150_hws static
  clk: samsung: exynos-clkout: Assign .num before accessing .hws
  clk: rockchip: Add clock and reset driver for RK3506
  dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
  clk: actions: Fix discarding const qualifier by 'container_of' macro
  clk: spacemit: Set clk_hw_onecell_data::num before using flex array
  clk: visconti: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Remove definition of number of clocks
  clk: visconti: Do not define number of clocks in bindings
  clk: rockchip: Add clock controller for the RV1126B
  dt-bindings: clock, reset: Add support for rv1126b
  clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
  clk: qcom: x1e80100-dispcc: Add USB4 router link resets
  dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
  clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
  dt-bindings: clock: qcom: Add SM8750 video clock controller
  clk: qcom: branch: Extend invert logic for branch2 mem clocks
  ...
parents 67a454e6 6f172175
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+1 −2
Original line number Diff line number Diff line
@@ -64,8 +64,6 @@ allOf:
        reg:
          minItems: 2

        '#reset-cells': false

  - if:
      properties:
        compatible:
@@ -85,6 +83,7 @@ examples:
      reg = <0x1fa20000 0x400>,
            <0x1fb00000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };

  - |
+72 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ULP LPAV System Integration Module (SIM)

maintainers:
  - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

description:
  The i.MX8ULP LPAV subsystem contains a block control module known as
  SIM LPAV, which offers functionalities such as clock gating or reset
  line assertion/de-assertion.

properties:
  compatible:
    const: fsl,imx8ulp-sim-lpav

  reg:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: bus
      - const: core
      - const: plat

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  mux-controller:
    $ref: /schemas/mux/reg-mux.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - mux-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8ulp-clock.h>

    clock-controller@2da50000 {
        compatible = "fsl,imx8ulp-sim-lpav";
        reg = <0x2da50000 0x10000>;
        clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
                 <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
                 <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
        clock-names = "bus", "core", "plat";
        #clock-cells = <1>;
        #reset-cells = <1>;

        mux-controller {
            compatible = "reg-mux";
            #mux-control-cells = <1>;
            mux-reg-masks = <0x8 0x00000200>;
        };
    };
+3 −0
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ properties:
  "#clock-cells":
    const: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

+22 −14
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ properties:
    const: microchip,mpfs-clkcfg

  reg:
    items:
    oneOf:
      - items:
          - description: |
              clock config registers:
              These registers contain enable, reset & divider tables for the, cpu,
@@ -32,6 +33,12 @@ properties:
              mss pll dri registers:
              Block of registers responsible for dynamic reconfiguration of the mss
              pll
        deprecated: true
      - items:
          - description: |
              mss pll dri registers:
              Block of registers responsible for dynamic reconfiguration of the mss
              pll

  clocks:
    maxItems: 1
@@ -69,11 +76,12 @@ examples:
  - |
    #include <dt-bindings/clock/microchip,mpfs-clock.h>
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
            clkcfg: clock-controller@20002000 {
            #address-cells = <1>;
            #size-cells = <1>;

            clkcfg: clock-controller@3E001000 {
                compatible = "microchip,mpfs-clkcfg";
                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
                reg = <0x3E001000 0x1000>;
                clocks = <&ref>;
                #clock-cells = <1>;
        };
+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties:
  compatible:
    enum:
      - qcom,glymur-rpmh-clk
      - qcom,kaanapali-rpmh-clk
      - qcom,milos-rpmh-clk
      - qcom,qcs615-rpmh-clk
      - qcom,qdu1000-rpmh-clk
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