Commit baf172cc authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets 



The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated
header file.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 354fc6c5

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+1 −0
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@@ -30,6 +30,7 @@ 
#include "phy-qcom-qmp-pcs-pcie-v5.h"

#include "phy-qcom-qmp-pcs-pcie-v5_20.h"

#include "phy-qcom-qmp-pcs-pcie-v6.h"

#include "phy-qcom-qmp-pcs-pcie-v6_20.h"

#include "phy-qcom-qmp-pcie-qhp.h"



/* QPHY_SW_RESET bit */

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h

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+23 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_

#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_



/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */

#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2		0x00c

#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG		0x018

#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE	0x01c

#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS		0x090

#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1			0x0a0

#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5			0x108

#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN			0x15c

#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1	0x17c

#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3	0x184

#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5	0x18c

#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5		0x1ac

#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5		0x1c0



#endif