Commit bbc6a829 authored Jun 25, 2025 by Niklas Cassel Committed by Manivannan Sadhasivam Jun 25, 2025

PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS



Macro PCIE_RESET_CONFIG_DEVICE_WAIT_MS was added to pci.h in commit
d5ceb949 ("PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time
value").

Later, in commit 70a7bfb1 ("PCI: rockchip-host: Wait 100ms after reset
before starting configuration"), PCIE_T_RRS_READY_MS was added to pci.h.

These macros are duplicates, and represent the exact same delay in the
PCIe specification.

Since the comment above PCIE_RESET_CONFIG_WAIT_MS is strictly more correct
than the comment above PCIE_T_RRS_READY_MS, change rockchip-host to use
PCIE_RESET_CONFIG_WAIT_MS, and remove PCIE_T_RRS_READY_MS, as
rockchip-host is the only user of this macro.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Link: https://patch.msgid.link/20250625102347.1205584-11-cassel@kernel.org

parent 817f9897

drivers/pci/controller/pcie-rockchip-host.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -325,7 +325,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
		msleep(PCIE_T_PVPERL_MS);
		gpiod_set_value_cansleep(rockchip->perst_gpio, 1);

		msleep(PCIE_T_RRS_READY_MS);
		msleep(PCIE_RESET_CONFIG_WAIT_MS);

		/* 500ms timeout value should be enough for Gen1/2 training */
		err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,

drivers/pci/pci.h

+0 −7

Original line number	Diff line number	Diff line
		@@ -35,13 +35,6 @@ struct pcie_tlp_log;
		*/
		#define PCIE_T_PERST_CLK_US 100

		/*
		* End of conventional reset (PERST# de-asserted) to first configuration
		* request (device able to respond with a "Request Retry Status" completion),
		* from PCIe r6.0, sec 6.6.1.
		*/
		#define PCIE_T_RRS_READY_MS 100

		/*
		* PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
		* Recommends 1ms to 10ms timeout to check L2 ready.