Commit becf4a77 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable() 



The bitmask << 16 is anyway set on both branches of if thus move it
before the if and set the lower bits of registers only in case clock is
enabled.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 17939df3

drivers/clk/renesas/rzg2l-cpg.c

+2 −3
Original line number Diff line number Diff line
@@ -909,10 +909,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) 
		enable ? "ON" : "OFF");

	spin_lock_irqsave(&priv->rmw_lock, flags);



	if (enable)

		value = (bitmask << 16) | bitmask;

	else

	value = bitmask << 16;

	if (enable)

		value |= bitmask;

	writel(value, priv->base + CLK_ON_R(reg));



	spin_unlock_irqrestore(&priv->rmw_lock, flags);