Unverified Commit bf6279b3 authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
Browse files

dt-bindings: cpus: add a thead vlen register length property 



Add a property analogous to the vlenb CSR so that software can detect
the vector length of each CPU prior to it being brought online.
Currently software has to assume that the vector length read from the
boot CPU applies to all possible CPUs. On T-Head CPUs implementing
pre-ratification vector, reading the th.vlenb CSR may produce an illegal
instruction trap, so this property is required on such systems.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-2-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent e576b7cb

Documentation/devicetree/bindings/riscv/cpus.yaml

+19 −0
Original line number Diff line number Diff line
@@ -26,6 +26,18 @@ description: | 
allOf:

  - $ref: /schemas/cpu.yaml#

  - $ref: extensions.yaml

  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - thead,c906

                - thead,c910

                - thead,c920

    then:

      properties:

        thead,vlenb: false



properties:

  compatible:
@@ -95,6 +107,13 @@ properties: 
    description:

      The blocksize in bytes for the Zicboz cache operations.



  thead,vlenb:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      VLEN/8, the vector register length in bytes. This property is required on

      thead systems where the vector register length is not identical on all harts, or

      the vlenb CSR is not available.



  # RISC-V has multiple properties for cache op block sizes as the sizes

  # differ between individual CBO extensions

  cache-op-block-size: false