Commit bffede38 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-02-03' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "A few more fixes this week, a bit more spread out though.

  We have a bunch of nouveau regression and stabilisation fixes, along
  with usual amdgpu, and i915. Otherwise just some minor misc ones:

  dma-fence:
   - fix signaling bit for private fences

  panel:
   - boe-tv101wum-nl6 disable fix

  nouveau:
   - gm20b acr regression fix
   - tu102 scrub status fix
   - tu102 wait for firmware fix

  i915:
   - Fixes for potential use-after-free and double-free
   - GuC locking and refcount fixes
   - Display's reference clock value fix

  amdgpu:
   - GC11 fixes
   - DCN 3.1.4 fixes
   - NBIO 4.3 fix
   - DCN 3.2 fixes
   - Properly handle additional cases where DCN is not supported
   - SMU13 fixes

  vc4:
   - fix CEC adapter names

  ssd130x:
   - fix display init regression"

* tag 'drm-fixes-2023-02-03' of git://anongit.freedesktop.org/drm/drm: (23 commits)
  drm/amd/display: Properly handle additional cases where DCN is not supported
  drm/amdgpu: Enable vclk dclk node for gc11.0.3
  drm/amd: Fix initialization for nbio 4.3.0
  drm/amdgpu: enable HDP SD for gfx 11.0.3
  drm/amd/pm: drop unneeded dpm features disablement for SMU 13.0.4/11
  drm/amd/display: Reset DMUB mailbox SW state after HW reset
  drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2
  drm/amd/display: Adjust downscaling limits for dcn314
  drm/amd/display: Add missing brackets in calculation
  drm/amdgpu: update wave data type to 3 for gfx11
  drm/panel: boe-tv101wum-nl6: Ensure DSI writes succeed during disable
  drm/nouveau/acr/gm20b: regression fixes
  drm/nouveau/fb/tu102-: fix register used to determine scrub status
  drm/nouveau/devinit/tu102-: wait for GFW_BOOT_PROGRESS == COMPLETED
  drm/i915/adlp: Fix typo for reference clock
  drm/i915: Fix potential bit_17 double-free
  drm/i915: Fix up locking around dumping requests lists
  drm/i915: Fix request ref counting during error capture & debugfs dump
  drm/i915/guc: Fix locking when searching for a hung request
  drm/i915: Avoid potential vm use-after-free
  ...
parents 0c272a1d f1a9e82a
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+1 −1
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ struct dma_fence *dma_fence_allocate_private_stub(void)
		       0, 0);

	set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
		&dma_fence_stub.flags);
		&fence->flags);

	dma_fence_signal(fence);

+2 −2
Original line number Diff line number Diff line
@@ -790,8 +790,8 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd,
	 * zero here */
	WARN_ON(simd != 0);

	/* type 2 wave data */
	dst[(*no_fields)++] = 2;
	/* type 3 wave data */
	dst[(*no_fields)++] = 3;
	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
+7 −1
Original line number Diff line number Diff line
@@ -337,7 +337,13 @@ const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = {

static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
{
	return;
	if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(4, 3, 0)) {
		uint32_t data;

		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
		data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
	}
}

static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
+2 −1
Original line number Diff line number Diff line
@@ -640,7 +640,8 @@ static int soc21_common_early_init(void *handle)
			AMD_CG_SUPPORT_GFX_CGCG |
			AMD_CG_SUPPORT_GFX_CGLS |
			AMD_CG_SUPPORT_REPEATER_FGCG |
			AMD_CG_SUPPORT_GFX_MGCG;
			AMD_CG_SUPPORT_GFX_MGCG |
			AMD_CG_SUPPORT_HDP_SD;
		adev->pg_flags = AMD_PG_SUPPORT_VCN |
			AMD_PG_SUPPORT_VCN_DPG |
			AMD_PG_SUPPORT_JPEG;
+11 −0
Original line number Diff line number Diff line
@@ -4501,6 +4501,17 @@ DEVICE_ATTR_WO(s3_debug);
static int dm_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_mode_info *mode_info = &adev->mode_info;
	struct atom_context *ctx = mode_info->atom_context;
	int index = GetIndexIntoMasterTable(DATA, Object_Header);
	u16 data_offset;

	/* if there is no object header, skip DM */
	if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
		adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
		dev_info(adev->dev, "No object header, skipping DM\n");
		return -ENOENT;
	}

	switch (adev->asic_type) {
#if defined(CONFIG_DRM_AMD_DC_SI)
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