Commit c171186c authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
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MIPS: csrc-r4k: Refine rating computation 



Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level mips_hpt_frequency.

Cap rating of csrc-r4k into 299 to ensure it doesn't go into
"Desired" range, given all the drama we have with CP0 count
registers (SMP sync, behaviour on wait etc).

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 04f38d1a

arch/mips/kernel/csrc-r4k.c

+2 −1
Original line number Diff line number Diff line
@@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) 
		return -ENXIO;



	/* Calculate a somewhat reasonable rating value */

	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;

	clocksource_mips.rating = 200;

	clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);



	/*

	 * R2 onwards makes the count accessible to user mode so it can be used