Commit c199b31a authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Jakub Kicinski
Browse files

ice: Add PHY OFFSET_READY register clearing 



Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.

Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: default avatarPucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-4-c082739bb6f6@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 0d80bbe2

drivers/net/ethernet/intel/ice/ice_ptp.c

+7 −4
Original line number Diff line number Diff line
@@ -1933,11 +1933,14 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) 
	struct ice_hw *hw = &pf->hw;

	int err;



	/* For Vernier mode, we need to recalibrate after new settime

	 * Start with disabling timestamp block

	/* For Vernier mode on E82X, we need to recalibrate after new settime.

	 * Start with marking timestamps as invalid.

	 */

	if (pf->ptp.port.link_up)

		ice_ptp_port_phy_stop(&pf->ptp.port);

	if (hw->ptp.phy_model == ICE_PHY_E82X) {

		err = ice_ptp_clear_phy_offset_ready_e82x(hw);

		if (err)

			dev_warn(ice_pf_to_dev(pf), "Failed to mark timestamps as invalid before settime\n");

	}



	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+34 −0
Original line number Diff line number Diff line
@@ -2409,6 +2409,40 @@ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 
	return 0;

}



/**

 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers

 * @hw: pointer to the HW struct

 *

 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted

 * and received timestamps as invalid.

 *

 * Return: 0 on success, other error codes when failed to write to PHY

 */

int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)

{

	u8 port;



	for (port = 0; port < hw->ptp.num_lports; port++) {

		int err;



		err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);

		if (err) {

			dev_warn(ice_hw_to_dev(hw),

				 "Failed to clear PHY TX_OFFSET_READY register\n");

			return err;

		}



		err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);

		if (err) {

			dev_warn(ice_hw_to_dev(hw),

				 "Failed to clear PHY RX_OFFSET_READY register\n");

			return err;

		}

	}



	return 0;

}



/**

 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time

 * @hw: pointer to the HW struct

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time); 
int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);

int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);

int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);

int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);

int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);

int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);

void ice_ptp_reset_ts_memory(struct ice_hw *hw);