Commit c233ec19 authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: Add num_slices_h to set_dto_dscclk signature 



Add the number of horizontal slices argument to allow configuring clock
based on slice number.

Reviewed-by: default avatarNevenko Stupar <nevenko.stupar@amd.com>
Signed-off-by: default avatarIlya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent def3f83e

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

+1 −1
Original line number Diff line number Diff line
@@ -727,7 +727,7 @@ void dccg401_init(struct dccg *dccg) 
	}

}



void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst)

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

+1 −2
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ void dccg401_disable_symclk32_le( 
		struct dccg *dccg,

		int hpo_le_inst);

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

void dccg401_set_ref_dscclk(struct dccg *dccg,

				uint32_t dsc_inst);

void dccg401_set_src_sel(
@@ -230,7 +230,6 @@ void dccg401_set_dp_dto( 
		const struct dp_dto_params *params);

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);

void dccg401_set_dtbclk_p_src(

		struct dccg *dccg,

		enum streamclk_source src,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

+4 −2
Original line number Diff line number Diff line
@@ -1063,15 +1063,17 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;



		if (should_use_dto_dscclk)

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst);

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;



			ASSERT(odm_dsc);

			if (!odm_dsc)

				continue;

			if (should_use_dto_dscclk)

				dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);

				dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

		}

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+1 −1
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ struct dccg_funcs { 
			struct dccg *dccg,

			enum streamclk_source src,

			uint32_t otg_inst);

	void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

	void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);

	void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

	void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

};

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+2 −2
Original line number Diff line number Diff line
@@ -843,14 +843,14 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;



		if (should_use_dto_dscclk)

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst);

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;



			if (should_use_dto_dscclk)

				dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);

				dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);

			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

		}