Unverified Commit c2c332d7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.19' of... 

Merge tag 'qcom-clk-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Qualcomm IPQ5424 Network Subsystem Clock Controller
 - Qualcomm SM8750 Video Clock Controller
 - Describe parent/child relationship among the Qualcomm Titan
   GDSCs on SM845, SM6350, SM7150, SM8250, SM8450, and SM8550
 - Define display subsystem reset signals for SM6350, SM7150, and SDM660
 - Add missing USB4 clocks and resets on Hamoa
 - Address a variety of smaller issues across the drivers, and a
   few more Kconfig dependency issues

* tag 'qcom-clk-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits)
  clk: qcom: x1e80100-dispcc: Add USB4 router link resets
  dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
  clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
  dt-bindings: clock: qcom: Add SM8750 video clock controller
  clk: qcom: branch: Extend invert logic for branch2 mem clocks
  clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
  clk: qcom: clk_mem_branch: add enable mask and invert flags
  clk: qcom: mmcc-sdm660: Add missing MDSS reset
  dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset
  clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers
  clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure
  dt-bindings: clock: qcom: Add Kaanapali Global clock controller
  dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali
  clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
  clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops
  clk: qcom: camcc-sm7150: Fix PLL config of PLL2
  clk: qcom: camcc-sm6350: Fix PLL config of PLL2
  clk: qcom: Add NSS clock controller driver for IPQ5424
  clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock
  ...
parents 3a866087 3664282f

Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml

+55 −8
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574

title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424



maintainers:

  - Bjorn Andersson <andersson@kernel.org>
@@ -12,21 +12,29 @@ maintainers: 


description: |

  Qualcomm networking sub system clock control module provides the clocks,

  resets on IPQ9574

  resets on IPQ9574 and IPQ5424



  See also::

  See also:

    include/dt-bindings/clock/qcom,ipq5424-nsscc.h

    include/dt-bindings/clock/qcom,ipq9574-nsscc.h

    include/dt-bindings/reset/qcom,ipq5424-nsscc.h

    include/dt-bindings/reset/qcom,ipq9574-nsscc.h



properties:

  compatible:

    const: qcom,ipq9574-nsscc

    enum:

      - qcom,ipq5424-nsscc

      - qcom,ipq9574-nsscc



  clocks:

    items:

      - description: Board XO source

      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source

      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source

      - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate

          can vary for different IPQ SoCs. For example, it is 1200 MHz on the

          IPQ9574 and 300 MHz on the IPQ5424.

      - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock

          rate can vary for different IPQ SoCs. For example, it is 353 MHz

          on the IPQ9574 and 375 MHz on the IPQ5424.

      - description: GCC GPLL0 OUT AUX clock source

      - description: Uniphy0 NSS Rx clock source

      - description: Uniphy0 NSS Tx clock source
@@ -42,8 +50,12 @@ properties: 
  clock-names:

    items:

      - const: xo

      - const: nss_1200

      - const: ppe_353

      - enum:

          - nss_1200

          - nss

      - enum:

          - ppe_353

          - ppe

      - const: gpll0_out

      - const: uniphy0_rx

      - const: uniphy0_tx
@@ -60,6 +72,40 @@ required: 


allOf:

  - $ref: qcom,gcc.yaml#

  - if:

      properties:

        compatible:

          const: qcom,ipq9574-nsscc

    then:

      properties:

        clock-names:

          items:

            - const: xo

            - const: nss_1200

            - const: ppe_353

            - const: gpll0_out

            - const: uniphy0_rx

            - const: uniphy0_tx

            - const: uniphy1_rx

            - const: uniphy1_tx

            - const: uniphy2_rx

            - const: uniphy2_tx

            - const: bus

    else:

      properties:

        clock-names:

          items:

            - const: xo

            - const: nss

            - const: ppe

            - const: gpll0_out

            - const: uniphy0_rx

            - const: uniphy0_tx

            - const: uniphy1_rx

            - const: uniphy1_tx

            - const: uniphy2_rx

            - const: uniphy2_tx

            - const: bus



unevaluatedProperties: false
@@ -94,5 +140,6 @@ examples: 
                    "bus";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #interconnect-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
  compatible:

    enum:

      - qcom,glymur-rpmh-clk

      - qcom,kaanapali-rpmh-clk

      - qcom,milos-rpmh-clk

      - qcom,qcs615-rpmh-clk

      - qcom,qdu1000-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml

+4 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Video Clock & Reset Controller on SM8450



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Taniya Das <taniya.das@oss.qualcomm.com>

  - Jagadeesh Kona <quic_jkona@quicinc.com>



description: |
@@ -17,6 +17,7 @@ description: | 
  See also:

    include/dt-bindings/clock/qcom,sm8450-videocc.h

    include/dt-bindings/clock/qcom,sm8650-videocc.h

    include/dt-bindings/clock/qcom,sm8750-videocc.h



properties:

  compatible:
@@ -25,6 +26,7 @@ properties: 
      - qcom,sm8475-videocc

      - qcom,sm8550-videocc

      - qcom,sm8650-videocc

      - qcom,sm8750-videocc

      - qcom,x1e80100-videocc



  clocks:
@@ -61,6 +63,7 @@ allOf: 
            enum:

              - qcom,sm8450-videocc

              - qcom,sm8550-videocc

              - qcom,sm8750-videocc

    then:

      required:

        - required-opps

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
    items:

      - enum:

          - qcom,glymur-tcsr

          - qcom,kaanapali-tcsr

          - qcom,milos-tcsr

          - qcom,sar2130p-tcsr

          - qcom,sm8550-tcsr

Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml

+6 −2
Original line number Diff line number Diff line
@@ -13,11 +13,15 @@ description: | 
  Qualcomm global clock control module provides the clocks, resets and power

  domains on SM8750



  See also: include/dt-bindings/clock/qcom,sm8750-gcc.h

  See also:

    include/dt-bindings/clock/qcom,kaanapali-gcc.h

    include/dt-bindings/clock/qcom,sm8750-gcc.h



properties:

  compatible:

    const: qcom,sm8750-gcc

    enum:

      - qcom,kaanapali-gcc

      - qcom,sm8750-gcc



  clocks:

    items: