Unverified Commit c30cc9ff authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next 

* clk-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 132MHz

* clk-thead:
  clk: thead: th1520-ap: Describe mux clocks with clk_mux
  clk: thead: th1520-ap: Correctly refer the parent of osc_12m
  clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED

* clk-microchip:
  clk: at91: sam9x7: update pll clk ranges

* clk-imx:
  MAINTAINERS: Update i.MX Clock Entry
  clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
  clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
  clk: imx95-blk-ctl: Fix synchronous abort
  dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data

* clk-qcom: (65 commits)
  dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom: Remove double colon from description
  clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Video Clock Controller
  clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos GPU Clock Controller
  clk: qcom: Add Display Clock controller (DISPCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Display Clock Controller
  clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Camera Clock Controller
  clk: qcom: Add Global Clock controller (GCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Global Clock Controller
  clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
  clk: qcom: gcc-x1e80100: Add missing video resets
  dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
  clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
  clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
  ...
parents e3abdd18 a0a6f598 853a7a63 53afec24 f46c06a3 be72da73

Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml

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Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ properties: 
  compatible:

    items:

      - enum:

          - nxp,imx94-display-csr

          - nxp,imx94-lvds-csr

          - nxp,imx95-camera-csr

          - nxp,imx95-display-csr

          - nxp,imx95-hsio-blk-ctl

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

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@@ -24,6 +24,8 @@ description: 
properties:

  compatible:

    enum:

      - qcom,ipq5018-cmn-pll

      - qcom,ipq5424-cmn-pll

      - qcom,ipq9574-cmn-pll



  reg:

Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,milos-camcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Camera Clock & Reset Controller on Milos



maintainers:

  - Luca Weiss <luca.weiss@fairphone.com>



description: |

  Qualcomm camera clock control module provides the clocks, resets and power

  domains on Milos.



  See also: include/dt-bindings/clock/qcom,milos-camcc.h



properties:

  compatible:

    const: qcom,milos-camcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: Camera AHB clock from GCC



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,milos-gcc.h>

    clock-controller@adb0000 {

        compatible = "qcom,milos-camcc";

        reg = <0x0adb0000 0x40000>;

        clocks = <&bi_tcxo_div2>,

                 <&sleep_clk>,

                 <&gcc GCC_CAMERA_AHB_CLK>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller on Milos



maintainers:

  - Luca Weiss <luca.weiss@fairphone.com>



description: |

  Qualcomm display clock control module provides the clocks, resets and power

  domains on Milos.



  See also: include/dt-bindings/clock/qcom,milos-dispcc.h



properties:

  compatible:

    const: qcom,milos-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: Display's AHB clock

      - description: GPLL0 source from GCC

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY0

      - description: Link clock from DP PHY0

      - description: VCO DIV clock from DP PHY0



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,milos-gcc.h>

    #include <dt-bindings/phy/phy-qcom-qmp.h>

    clock-controller@af00000 {

        compatible = "qcom,milos-dispcc";

        reg = <0x0af00000 0x20000>;

        clocks = <&bi_tcxo_div2>,

                 <&sleep_clk>,

                 <&gcc GCC_DISP_AHB_CLK>,

                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,

                 <&mdss_dsi0_phy 0>,

                 <&mdss_dsi0_phy 1>,

                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,

                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on Milos



maintainers:

  - Luca Weiss <luca.weiss@fairphone.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on Milos.



  See also: include/dt-bindings/clock/qcom,milos-gcc.h



properties:

  compatible:

    const: qcom,milos-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

        compatible = "qcom,milos-gcc";

        reg = <0x00100000 0x1f4200>;

        clocks = <&rpmhcc RPMH_CXO_CLK>,

                 <&sleep_clk>,

                 <&pcie0_phy>,

                 <&pcie1_phy>,

                 <&ufs_mem_phy 0>,

                 <&ufs_mem_phy 1>,

                 <&ufs_mem_phy 2>,

                 <&usb_1_qmpphy>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;

    };



...