Commit c3dddd60 authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Enable devcoredump for JPEG4_0_0 



Add register list and enable devcoredump for JPEG4_0_0

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 358b3774

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

+23 −1
Original line number Diff line number Diff line
@@ -36,13 +36,28 @@ 


#define regUVD_JPEG_PITCH_INTERNAL_OFFSET                  0x401f



static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = {

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),

	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),

};



static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);

static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);

static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);

static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,

				enum amd_powergating_state state);

static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);



static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring);



/**
@@ -123,6 +138,11 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 
	r = amdgpu_jpeg_ras_sw_init(adev);

	if (r)

		return r;



	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0));

	if (r)

		return r;



	/* TODO: Add queue reset mask when FW fully supports it */

	adev->jpeg.supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
@@ -717,6 +737,8 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 
	.wait_for_idle = jpeg_v4_0_wait_for_idle,

	.set_clockgating_state = jpeg_v4_0_set_clockgating_state,

	.set_powergating_state = jpeg_v4_0_set_powergating_state,

	.dump_ip_state = amdgpu_jpeg_dump_ip_state,

	.print_ip_state = amdgpu_jpeg_print_ip_state,

};



static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {