Commit c3f18746 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.7-tag2' of... 

Merge tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pulll more Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the RZ/G3S (R9A08G045) SoC
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: Add minimal boot support for RZ/G3S SoC
  clk: renesas: rzg2l: Add divider clock for RZ/G3S
  clk: renesas: rzg2l: Refactor SD mux driver
  clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
  clk: renesas: rzg2l: Add struct clk_hw_data
  clk: renesas: rzg2l: Add support for RZ/G3S PLL
  clk: renesas: rzg2l: Remove critical area
  clk: renesas: rzg2l: Fix computation formula
  clk: renesas: rzg2l: Trust value returned by hardware
  clk: renesas: rzg2l: Lock around writes to mux register
  clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
  clk: renesas: rcar-gen3: Extend SDnH divider table
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
parents 29521343 4bce4bed

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties: 
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a08g045-cpg # RZ/G3S

      - renesas,r9a09g011-cpg # RZ/V2M



  reg:

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ config CLK_RENESAS 
	select CLK_R9A07G043 if ARCH_R9A07G043

	select CLK_R9A07G044 if ARCH_R9A07G044

	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_R9A08G045 if ARCH_R9A08G045

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_SH73A0 if ARCH_SH73A0
@@ -179,6 +180,10 @@ config CLK_R9A07G054 
	bool "RZ/V2L clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A08G045

	bool "RZ/G3S clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A09G011

	bool "RZ/V2M clock support" if COMPILE_TEST

	select CLK_RZG2L
@@ -215,7 +220,7 @@ config CLK_RCAR_USB2_CLOCK_SEL 
	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST

	bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o 
obj-$(CONFIG_CLK_R9A07G043)		+= r9a07g043-cpg.o

obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o

obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o

drivers/clk/renesas/r9a07g043-cpg.c

+17 −2
Original line number Diff line number Diff line
@@ -14,6 +14,17 @@ 


#include "rzg2l-cpg.h"



/* Specific registers. */

#define CPG_PL2SDHI_DSEL	(0x218)



/* Clock select configuration. */

#define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

#define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)



/* Clock status configuration. */

#define SEL_SDHI0_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)

#define SEL_SDHI1_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
@@ -78,6 +89,8 @@ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 
static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };



static const u32 mtable_sdhi[] = { 1, 2, 3 };



static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal", CLK_EXTAL),
@@ -123,8 +136,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),

	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),

	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi),

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,

		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,

		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),

	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),

};

drivers/clk/renesas/r9a07g044-cpg.c

+17 −2
Original line number Diff line number Diff line
@@ -15,6 +15,17 @@ 


#include "rzg2l-cpg.h"



/* Specific registers. */

#define CPG_PL2SDHI_DSEL	(0x218)



/* Clock select configuration. */

#define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

#define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)



/* Clock status configuration. */

#define SEL_SDHI0_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)

#define SEL_SDHI1_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
@@ -98,6 +109,8 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const u32 mtable_sdhi[] = { 1, 2, 3 };



static const struct {

	struct cpg_core_clk common[56];

#ifdef CONFIG_CLK_R9A07G054
@@ -163,8 +176,10 @@ static const struct { 
		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),

		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),

		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),

		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,

			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,

			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),

		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),