Commit c51a37ff authored by Michal Wilczynski's avatar Michal Wilczynski Committed by Drew Fustini
Browse files

clk: thead: Correct parent for DPU pixel clocks 



The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to
the video_pll_clk.

According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from
"DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to
the `dpu0_clk` clock, which is a divider whose parent is the
`dpu0_pll_clk`.

This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk`
to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its
correct source, `dpu1_clk`.

Fixes: 50d4b157 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC")
Reported-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Signed-off-by: default avatarMichal Wilczynski <m.wilczynski@samsung.com>
[Icenowy: add Drew's R-b and rebased atop ccu_gate refactor]
Reviewed-by: default avatarDrew Fustini <fustini@kernel.org>
Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Signed-off-by: default avatarDrew Fustini <fustini@kernel.org>
parent 9e99b992

drivers/clk/thead/clk-th1520-ap.c

+10 −2
Original line number Diff line number Diff line
@@ -761,6 +761,10 @@ static struct ccu_div dpu0_clk = { 
	},

};



static const struct clk_parent_data dpu0_clk_pd[] = {

	{ .hw = &dpu0_clk.common.hw }

};



static struct ccu_div dpu1_clk = {

	.div		= TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),

	.common		= {
@@ -773,6 +777,10 @@ static struct ccu_div dpu1_clk = { 
	},

};



static const struct clk_parent_data dpu1_clk_pd[] = {

	{ .hw = &dpu1_clk.common.hw }

};



static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref",

			   &video_pll_clk.common.hw, 4, 1, 0);
@@ -853,9 +861,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, 
static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",

		video_pll_clk_pd, 0x0, 4, 0);

static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",

		video_pll_clk_pd, 0x0, 5, 0);

		dpu0_clk_pd, 0x0, 5, 0);

static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",

		video_pll_clk_pd, 0x0, 6, 0);

		dpu1_clk_pd, 0x0, 6, 0);

static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0,

		7, 0);

static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0,