Commit c7183ff5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next 

* clk-assigned-rates:
  clk: clk-conf: support assigned-clock-rates-u64

* clk-renesas: (34 commits)
  clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
  clk: renesas: rzv2h: Add support for dynamic switching divider clocks
  clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
  dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
  clk: renesas: r8a779h0: Add CANFD clock
  clk: renesas: Add RZ/V2H(P) CPG driver
  clk: renesas: Add family-specific clock driver for RZ/V2H(P)
  dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
  clk: renesas: r8a779h0: Add PWM clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
  clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
  clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
  clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
  clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
  clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
  clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
  clk: renesas: r8a779a0: Use defines for PLL control registers
  clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
  clk: renesas: rcar-gen4: Add support for fixed variable PLLs
  clk: renesas: rcar-gen4: Add support for variable fractional PLLs
  ...

* clk-scmi:
  clk: scmi: add is_prepared hook
parents a2b88026 965e0637 f3721310 fc953d40

Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml

+6 −2
Original line number Diff line number Diff line
@@ -32,12 +32,16 @@ properties: 
  reg:

    maxItems: 1



  clocks: true

  clocks:

    minItems: 1

    maxItems: 3



  '#clock-cells':

    const: 1



  clock-output-names: true

  clock-output-names:

    minItems: 3

    maxItems: 17



  renesas,mode:

    description: Board-specific settings of the MD_CK* bits on R-Mobile A1

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ properties: 
      - renesas,r8a7745-cpg-mssr  # RZ/G1E

      - renesas,r8a77470-cpg-mssr # RZ/G1C

      - renesas,r8a774a1-cpg-mssr # RZ/G2M

      - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0

      - renesas,r8a774b1-cpg-mssr # RZ/G2N

      - renesas,r8a774c0-cpg-mssr # RZ/G2E

      - renesas,r8a774e1-cpg-mssr # RZ/G2H

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

0 → 100644
+80 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: AUDIO_EXTAL clock input

      - description: RTXIN clock input

      - description: QEXTAL clock input



  clock-names:

    items:

      - const: audio_extal

      - const: rtxin

      - const: qextal



  '#clock-cells':

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the

        calculation is (1 * 16 + 3) = 0x13.

    const: 2



  '#power-domain-cells':

    const: 0



  '#reset-cells':

    description:

      The single reset specifier cell must be the reset number. The reset number

      is calculated as the reset register offset index multiplied by 16, plus the

      actual bit in the register used to reset the specific IP block. For example,

      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@10420000 {

        compatible = "renesas,r9a09g057-cpg";

        reg = <0x10420000 0x10000>;

        clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;

        clock-names = "audio_extal", "rtxin", "qextal";

        #clock-cells = <2>;

        #power-domain-cells = <0>;

        #reset-cells = <1>;

    };

drivers/clk/clk-conf.c

+38 −5
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/device.h>

#include <linux/of.h>

#include <linux/printk.h>

#include <linux/slab.h>



static int __set_clk_parents(struct device_node *node, bool clk_supplier)

{
@@ -81,11 +82,44 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) 
static int __set_clk_rates(struct device_node *node, bool clk_supplier)

{

	struct of_phandle_args clkspec;

	int rc, index = 0;

	int rc, count, count_64, index;

	struct clk *clk;

	u32 rate;

	u64 *rates_64 __free(kfree) = NULL;

	u32 *rates __free(kfree) = NULL;



	count = of_property_count_u32_elems(node, "assigned-clock-rates");

	count_64 = of_property_count_u64_elems(node, "assigned-clock-rates-u64");

	if (count_64 > 0) {

		count = count_64;

		rates_64 = kcalloc(count, sizeof(*rates_64), GFP_KERNEL);

		if (!rates_64)

			return -ENOMEM;



		rc = of_property_read_u64_array(node,

						"assigned-clock-rates-u64",

						rates_64, count);

	} else if (count > 0) {

		rates = kcalloc(count, sizeof(*rates), GFP_KERNEL);

		if (!rates)

			return -ENOMEM;



		rc = of_property_read_u32_array(node, "assigned-clock-rates",

						rates, count);

	} else {

		return 0;

	}



	if (rc)

		return rc;



	for (index = 0; index < count; index++) {

		unsigned long rate;



		if (rates_64)

			rate = rates_64[index];

		else

			rate = rates[index];



	of_property_for_each_u32(node, "assigned-clock-rates", rate) {

		if (rate) {

			rc = of_parse_phandle_with_args(node, "assigned-clocks",

					"#clock-cells",	index, &clkspec);
@@ -112,12 +146,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) 


			rc = clk_set_rate(clk, rate);

			if (rc < 0)

				pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",

				pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n",

				       __clk_get_name(clk), rate, rc,

				       clk_get_rate(clk));

			clk_put(clk);

		}

		index++;

	}

	return 0;

}

drivers/clk/clk-scmi.c

+14 −2
Original line number Diff line number Diff line
@@ -156,13 +156,13 @@ static void scmi_clk_atomic_disable(struct clk_hw *hw) 
	scmi_proto_clk_ops->disable(clk->ph, clk->id, ATOMIC);

}



static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)

static int __scmi_clk_is_enabled(struct clk_hw *hw, bool atomic)

{

	int ret;

	bool enabled = false;

	struct scmi_clk *clk = to_scmi_clk(hw);



	ret = scmi_proto_clk_ops->state_get(clk->ph, clk->id, &enabled, ATOMIC);

	ret = scmi_proto_clk_ops->state_get(clk->ph, clk->id, &enabled, atomic);

	if (ret)

		dev_warn(clk->dev,

			 "Failed to get state for clock ID %d\n", clk->id);
@@ -170,6 +170,16 @@ static int scmi_clk_atomic_is_enabled(struct clk_hw *hw) 
	return !!enabled;

}



static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)

{

	return __scmi_clk_is_enabled(hw, ATOMIC);

}



static int scmi_clk_is_enabled(struct clk_hw *hw)

{

	return __scmi_clk_is_enabled(hw, NOT_ATOMIC);

}



static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)

{

	int ret;
@@ -285,6 +295,8 @@ scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key) 


	if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))

		ops->is_enabled = scmi_clk_atomic_is_enabled;

	else

		ops->is_prepared = scmi_clk_is_enabled;



	/* Rate ops */

	ops->recalc_rate = scmi_clk_recalc_rate;