Commit c781a72f authored by Namhyung Kim's avatar Namhyung Kim
Browse files

tools/include: Sync x86 asm/msr-index.h with the kernel sources 



To pick up the changes from:

  8076fcde ("x86/rfds: Mitigate Register File Data Sampling (RFDS)")
  d7b69b59 ("x86/sev: Dump SEV_STATUS")
  cd6df3f3 ("x86/cpu: Add MSR numbers for FRED configuration")
  216d106c ("x86/sev: Add SEV-SNP host initialization support")

This should address these tools/perf build warnings:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240408185520.1550865-8-namhyung@kernel.org
parent 978f2a60

tools/arch/x86/include/asm/msr-index.h

+51 −23
Original line number Diff line number Diff line
@@ -176,6 +176,14 @@ 
						 * CPU is not vulnerable to Gather

						 * Data Sampling (GDS).

						 */

#define ARCH_CAP_RFDS_NO		BIT(27)	/*

						 * Not susceptible to Register

						 * File Data Sampling.

						 */

#define ARCH_CAP_RFDS_CLEAR		BIT(28)	/*

						 * VERW clears CPU Register

						 * File.

						 */



#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR
@@ -605,34 +613,47 @@ 
#define MSR_AMD64_SEV_ES_GHCB		0xc0010130

#define MSR_AMD64_SEV			0xc0010131

#define MSR_AMD64_SEV_ENABLED_BIT	0

#define MSR_AMD64_SEV_ES_ENABLED_BIT	1

#define MSR_AMD64_SEV_SNP_ENABLED_BIT	2

#define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)

#define MSR_AMD64_SEV_ES_ENABLED_BIT	1

#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)

#define MSR_AMD64_SEV_SNP_ENABLED_BIT	2

#define MSR_AMD64_SEV_SNP_ENABLED	BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)



/* SNP feature bits enabled by the hypervisor */

#define MSR_AMD64_SNP_VTOM			BIT_ULL(3)

#define MSR_AMD64_SNP_REFLECT_VC		BIT_ULL(4)

#define MSR_AMD64_SNP_RESTRICTED_INJ		BIT_ULL(5)

#define MSR_AMD64_SNP_ALT_INJ			BIT_ULL(6)

#define MSR_AMD64_SNP_DEBUG_SWAP		BIT_ULL(7)

#define MSR_AMD64_SNP_PREVENT_HOST_IBS		BIT_ULL(8)

#define MSR_AMD64_SNP_BTB_ISOLATION		BIT_ULL(9)

#define MSR_AMD64_SNP_VMPL_SSS			BIT_ULL(10)

#define MSR_AMD64_SNP_SECURE_TSC		BIT_ULL(11)

#define MSR_AMD64_SNP_VMGEXIT_PARAM		BIT_ULL(12)

#define MSR_AMD64_SNP_IBS_VIRT			BIT_ULL(14)

#define MSR_AMD64_SNP_VMSA_REG_PROTECTION	BIT_ULL(16)

#define MSR_AMD64_SNP_SMT_PROTECTION		BIT_ULL(17)



/* SNP feature bits reserved for future use. */

#define MSR_AMD64_SNP_VTOM_BIT		3

#define MSR_AMD64_SNP_VTOM		BIT_ULL(MSR_AMD64_SNP_VTOM_BIT)

#define MSR_AMD64_SNP_REFLECT_VC_BIT	4

#define MSR_AMD64_SNP_REFLECT_VC	BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)

#define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5

#define MSR_AMD64_SNP_RESTRICTED_INJ	BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)

#define MSR_AMD64_SNP_ALT_INJ_BIT	6

#define MSR_AMD64_SNP_ALT_INJ		BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)

#define MSR_AMD64_SNP_DEBUG_SWAP_BIT	7

#define MSR_AMD64_SNP_DEBUG_SWAP	BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)

#define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8

#define MSR_AMD64_SNP_PREVENT_HOST_IBS	BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT)

#define MSR_AMD64_SNP_BTB_ISOLATION_BIT	9

#define MSR_AMD64_SNP_BTB_ISOLATION	BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT)

#define MSR_AMD64_SNP_VMPL_SSS_BIT	10

#define MSR_AMD64_SNP_VMPL_SSS		BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT)

#define MSR_AMD64_SNP_SECURE_TSC_BIT	11

#define MSR_AMD64_SNP_SECURE_TSC	BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT)

#define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT	12

#define MSR_AMD64_SNP_VMGEXIT_PARAM	BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT)

#define MSR_AMD64_SNP_RESERVED_BIT13	BIT_ULL(13)

#define MSR_AMD64_SNP_IBS_VIRT_BIT	14

#define MSR_AMD64_SNP_IBS_VIRT		BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT)

#define MSR_AMD64_SNP_RESERVED_BIT15	BIT_ULL(15)

#define MSR_AMD64_SNP_RESERVED_MASK		GENMASK_ULL(63, 18)

#define MSR_AMD64_SNP_VMSA_REG_PROT_BIT	16

#define MSR_AMD64_SNP_VMSA_REG_PROT	BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)

#define MSR_AMD64_SNP_SMT_PROT_BIT	17

#define MSR_AMD64_SNP_SMT_PROT		BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)

#define MSR_AMD64_SNP_RESV_BIT		18

#define MSR_AMD64_SNP_RESERVED_MASK	GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)



#define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f



#define MSR_AMD64_RMP_BASE		0xc0010132

#define MSR_AMD64_RMP_END		0xc0010133



/* AMD Collaborative Processor Performance Control MSRs */

#define MSR_AMD_CPPC_CAP1		0xc00102b0

#define MSR_AMD_CPPC_ENABLE		0xc00102b1
@@ -721,6 +742,13 @@ 
#define MSR_AMD64_SYSCFG		0xc0010010

#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23

#define MSR_AMD64_SYSCFG_MEM_ENCRYPT	BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)

#define MSR_AMD64_SYSCFG_SNP_EN_BIT	24

#define MSR_AMD64_SYSCFG_SNP_EN		BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT)

#define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25

#define MSR_AMD64_SYSCFG_SNP_VMPL_EN	BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT)

#define MSR_AMD64_SYSCFG_MFDM_BIT	19

#define MSR_AMD64_SYSCFG_MFDM		BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT)



#define MSR_K8_INT_PENDING_MSG		0xc0010055

/* C1E active bits in int pending message */

#define K8_INTP_C1E_ACTIVE_MASK		0x18000000