Commit c7c703e4 authored by Karthi Kandasamy's avatar Karthi Kandasamy Committed by Alex Deucher
Browse files

drm/amd/display: Ensure correct GFX tiling info passed to DML 



[Why]
To ensure DML validation receives the correct tiling information,
such as swizzle mode or array mode, based on the active GFX format

[How]
- For new GFX format passed swizzle_mode to DML.
- For legacy GFX format passed array_mode to DML.
- Dynamically determined the appropriate tiling info based on the
  active GFX format.

[Description]
This commit ensures that the correct GFX tiling information is passed
to DML. Depending on the active GFX format, the appropriate tiling info
is passed to DML. This change accommodates the different GFX formats
supported by latest platforms, ensuring compatibility and proper
DML validation.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarKarthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 080950cb

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

+3 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_in 
		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);



		tiling_info->gfxversion = DcGfxVersion8;

		/* XXX fix me for VI */

		tiling_info->gfx8.num_banks = num_banks;

		tiling_info->gfx8.array_mode =
@@ -317,6 +318,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg 


	amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);

	tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);

	tiling_info->gfxversion = DcGfxVersion9;



	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {

		uint64_t dcc_address = afb->address + afb->base.offsets[1];
@@ -369,6 +371,7 @@ static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amd 
	amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);



	tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);

	tiling_info->gfxversion = DcGfxAddr3;



	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {

		int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+13 −3
Original line number Diff line number Diff line
@@ -721,11 +721,21 @@ static void populate_dml21_surface_config_from_plane_state( 
	surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_blks_c;

	surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch;

	surface->dcc.plane1.pitch = plane_state->dcc.meta_pitch_c;

	if (in_dc->ctx->dce_version < DCN_VERSION_4_01) {

		/* needed for N-1 testing */



	// Update swizzle / array mode based on the gfx_format

	switch (plane_state->tiling_info.gfxversion) {

	case DcGfxVersion7:

	case DcGfxVersion8:

		// Placeholder for programming the array_mode

		break;

	case DcGfxVersion9:

	case DcGfxVersion10:

	case DcGfxVersion11:

		surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle);

	} else {

		break;

	case DcGfxAddr3:

		surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle);

		break;

	}

}

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

+8 −1
Original line number Diff line number Diff line
@@ -1752,6 +1752,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc, 
	return out;

}



enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)

{

	plane_state->tiling_info.gfxversion = DcGfxVersion9;

	dcn20_patch_unknown_plane_state(plane_state);

	return DC_OK;

}





static struct resource_funcs dcn35_res_pool_funcs = {

	.destroy = dcn35_destroy_resource_pool,
@@ -1775,7 +1782,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { 
	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,

	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,

	.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,

	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,

	.get_panel_config_defaults = dcn35_get_panel_config_defaults,

	.get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,

	.get_det_buffer_size = dcn31_get_det_buffer_size,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 


extern struct _vcs_dpi_ip_params_st dcn3_5_ip;

extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc;

enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);



struct dcn35_resource_pool {

	struct resource_pool base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1754,7 +1754,7 @@ static struct resource_funcs dcn351_res_pool_funcs = { 
	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,

	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,

	.update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,

	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,

	.get_panel_config_defaults = dcn35_get_panel_config_defaults,

	.get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,

	.get_det_buffer_size = dcn31_get_det_buffer_size,