Commit c7eb9c5e authored by Niklas Cassel's avatar Niklas Cassel Committed by Manivannan Sadhasivam
Browse files

PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ 



Per PCIe r6.0, sec 6.6.1, software must generally wait a minimum of
100ms (PCIE_RESET_CONFIG_WAIT_MS) after Link training completes before
sending a Configuration Request.

Prior to ec9fd499 ("PCI: dw-rockchip: Don't wait for link since
we can detect Link Up"), dw-rockchip used dw_pcie_wait_for_link(),
which waited between 0 and 90ms after the link came up before we
enumerate the bus, and this was apparently enough for most devices.

After ec9fd499, rockchip_pcie_rc_sys_irq_thread() started
enumeration immediately when handling the link-up IRQ, and devices
(e.g., Laszlo Fiat's PLEXTOR PX-256M8PeGN NVMe SSD) may not be ready
to handle config requests yet.

Delay PCIE_RESET_CONFIG_WAIT_MS after the link-up IRQ before starting
enumeration.

Fixes: 0e898eb8 ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
Signed-off-by: default avatarNiklas Cassel <cassel@kernel.org>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Reviewed-by: default avatarWilfred Mallawa <wilfred.mallawa@wdc.com>
Cc: Laszlo Fiat <laszlo.fiat@proton.me>
Link: https://patch.msgid.link/20250625102347.1205584-12-cassel@kernel.org
parent bbc6a829

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+1 −0
Original line number Diff line number Diff line
@@ -458,6 +458,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) 


	if (reg & PCIE_RDLH_LINK_UP_CHGED) {

		if (rockchip_pcie_link_up(pci)) {

			msleep(PCIE_RESET_CONFIG_WAIT_MS);

			dev_dbg(dev, "Received Link up event. Starting enumeration!\n");

			/* Rescan the bus to enumerate endpoint devices */

			pci_lock_rescan_remove();