Commit c88ab940 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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pinctrl: renesas: rzg2l: Fix SMT register cache handling 



Store SMT register cache per bank instead of using a single array.

On RZ/V2H(P), RZ/V2N, and RZ/G3E, the SMT register is split across two
32-bit registers: bits 0/8/16/24 control pins 0-3, while pins 4-7 are
controlled by the corresponding bits in the next register.  The previous
implementation cached only a single SMT register, leading to incomplete
save/restore of SMT state.

Convert cache->smt to a per-bank array and allocate storage for both
halves.  Update suspend/resume handling to save and restore both SMT
registers when present.

Fixes: 837afa59 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6dba9b72

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+14 −7
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ struct rzg2l_pinctrl_reg_cache { 
	u32	*iolh[2];

	u32	*ien[2];

	u32	*pupd[2];

	u32	*smt;

	u32	*smt[2];

	u8	sd_ch[2];

	u8	eth_poc[2];

	u8	oen;
@@ -2737,10 +2737,6 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 
	if (!cache->pfc)

		return -ENOMEM;



	cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL);

	if (!cache->smt)

		return -ENOMEM;



	for (u8 i = 0; i < 2; i++) {

		u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
@@ -2759,6 +2755,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 
		if (!cache->pupd[i])

			return -ENOMEM;



		cache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]),

					     GFP_KERNEL);

		if (!cache->smt[i])

			return -ENOMEM;



		/* Allocate dedicated cache. */

		dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,

							sizeof(*dedicated_cache->iolh[i]),
@@ -3066,8 +3067,14 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen 
			}

		}



		if (has_smt)

			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);

		if (has_smt) {

			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off),

						 cache->smt[0][port]);

			if (pincnt >= 4) {

				RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4,

							 cache->smt[1][port]);

			}

		}

	}

}