Commit c954b6d3 authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
Browse files

phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650 



Add QMP PCIe PHY support for the SM8650 platform.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-6-a543a4c4b491@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 7c4bf8cb

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+65 −0
Original line number Diff line number Diff line
@@ -1909,6 +1909,35 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),

};



static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),

	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),

};



static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -3047,6 +3076,36 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 
	.has_nocsr_reset	= true,

};



static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {

	.lanes = 2,



	.offsets		= &qmp_pcie_offsets_v6_20,



	.tbls = {

		.serdes			= sm8550_qmp_gen4x2_pcie_serdes_tbl,

		.serdes_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),

		.tx			= sm8550_qmp_gen4x2_pcie_tx_tbl,

		.tx_num			= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),

		.rx			= sm8650_qmp_gen4x2_pcie_rx_tbl,

		.rx_num			= ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),

		.pcs			= sm8550_qmp_gen4x2_pcie_pcs_tbl,

		.pcs_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),

		.pcs_misc		= sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,

		.pcs_misc_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),

		.ln_shrd		= sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,

		.ln_shrd_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),

	},

	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= sm8550_qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

	.regs			= pciephy_v5_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,

	.has_nocsr_reset	= true,

};



static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {

	.lanes			= 2,

	.offsets		= &qmp_pcie_offsets_v5_20,
@@ -3820,6 +3879,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",

		.data = &sm8550_qmp_gen4x2_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",

		.data = &sm8550_qmp_gen3x2_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",

		.data = &sm8650_qmp_gen4x2_pciephy_cfg,

	},

	{ },

};