Commit cbbf0a75 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull mtd updates from Miquel Raynal:
 "MTD changes:

   - Apart from a binding conversion to yaml, only minor changes/small
     fixes have been merged.

  Raw NAND changes:

   - Minor fixes for various controller drivers like DMA mapping checks,
     better timing derivations or bitflip statistics.

   - some Hynix NAND flashes were not supporting read-retries, so don't
     even try to do it

  SPI NAND changes:

   - In order to support high-speed modes, certain chips need extra
     configuration like adding more dummy cycles. This is now possible,
     especially on Winbond chips.

   - Aside from that, Gigadevice gets support for a new chip (GD5F1GM9).

  SPI NOR changes:

   - A notable changes is the fix for exiting 4-byte addressing on
     Infineon SEMPER flashes. These flashes do not support the standard
     EX4B opcode (E9h), and use a vendor-specific opcode (B8h) instead.

   - There is also a fix for unlocking flashes that are write-protected
     at power-on. This was caused by using an uninitialized mtd_info in
     spi_nor_try_unlock_all()"

* tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (26 commits)
  mtd: spinand: winbond: Add comment about the maximum frequency
  mtd: spinand: winbond: Enable high-speed modes on w35n0xjw
  mtd: spinand: winbond: Enable high-speed modes on w25n0xjw
  mtd: spinand: Add a ->configure_chip() hook
  mtd: spinand: Add a frequency field to all READ_FROM_CACHE variants
  mtd: spinand: Fix macro alignment
  spi: spi-mem: Take into account the actual maximum frequency
  spi: spi-mem: Use picoseconds for calculating the op durations
  mtd: rawnand: atmel: set pmecc data setup time
  mtd: spinand: propagate spinand_wait() errors from spinand_write_page()
  mtd: rawnand: fsmc: Add missing check after DMA map
  mtd: rawnand: rockchip: Add missing check after DMA map
  mtd: rawnand: hynix: don't try read-retry on SLC NANDs
  mtd: rawnand: atmel: Fix dma_mapping_error() address
  mtd: nand: brcmnand: fix mtd corrected bits stat
  mtd: rawnand: renesas: Add missing check after DMA map
  mtd: spinand: gigadevice: Add support for GD5F1GM9 chips
  mtd: nand: brcmnand: replace manual string choices with standard helpers
  mtd: map: Don't use "proxy" headers
  mtd: spi-nor: Fix spi_nor_try_unlock_all()
  ...
parents 2d945dde 9cf9db88

Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ properties: 
          - pattern: "^((((micron|spansion|st),)?\

              (m25p(40|80|16|32|64|128)|\

              n25q(32b|064|128a11|128a13|256a|512a|164k)))|\

              atmel,at25df(321a|641|081a)|\

              atmel,at(25|26)df(321a|641|081a)|\

              everspin,mr25h(10|40|128|256)|\

              (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\

              (mxicy|macronix),mx25u(4033|4035)|\

Documentation/devicetree/bindings/mtd/nxp,lpc1773-spifi.yaml

0 → 100644
+74 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP SPI Flash Interface (SPIFI)



description:

  NXP SPIFI is a specialized SPI interface for serial Flash devices.

  It supports one Flash device with 1-, 2- and 4-bits width in SPI

  mode 0 or 3. The controller operates in either command or memory

  mode. In memory mode the Flash is accessible from the CPU as

  normal memory.



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    const: nxp,lpc1773-spifi



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: spifi

      - const: flash



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: spifi

      - const: reg



  resets:

    maxItems: 1



  spi-cpol:

    enum: [0, 3]



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clocks

  - clock-names



allOf:

  - $ref: /schemas/spi/spi-controller.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/lpc18xx-ccu.h>



    spi@40003000 {

        compatible = "nxp,lpc1773-spifi";

        reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;

        reg-names = "spifi", "flash";

        interrupts = <30>;

        clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;

        clock-names = "spifi", "reg";

        resets = <&rgu 53>;

    };

Documentation/devicetree/bindings/mtd/nxp-spifi.txt

deleted100644 → 0
+0 −58
Original line number Diff line number Diff line 
* NXP SPI Flash Interface (SPIFI)



NXP SPIFI is a specialized SPI interface for serial Flash devices.

It supports one Flash device with 1-, 2- and 4-bits width in SPI

mode 0 or 3. The controller operates in either command or memory

mode. In memory mode the Flash is accessible from the CPU as

normal memory.



Required properties:

  - compatible : Should be "nxp,lpc1773-spifi"

  - reg : the first contains the register location and length,

          the second contains the memory mapping address and length

  - reg-names: Should contain the reg names "spifi" and "flash"

  - interrupts : Should contain the interrupt for the device

  - clocks : The clocks needed by the SPIFI controller

  - clock-names : Should contain the clock names "spifi" and "reg"



Optional properties:

 - resets : phandle + reset specifier



The SPI Flash must be a child of the SPIFI node and must have a

compatible property as specified in bindings/mtd/jedec,spi-nor.txt



Optionally it can also contain the following properties.

 - spi-cpol : Controller only supports mode 0 and 3 so either

              both spi-cpol and spi-cpha should be present or

              none of them

 - spi-cpha : See above

 - spi-rx-bus-width : Used to select how many pins that are used

                      for input on the controller



See bindings/spi/spi-bus.txt for more information.



Example:

spifi: spifi@40003000 {

	compatible = "nxp,lpc1773-spifi";

	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;

	reg-names = "spifi", "flash";

	interrupts = <30>;

	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;

	clock-names = "spifi", "reg";

	resets = <&rgu 53>;



	flash@0 {

		compatible = "jedec,spi-nor";

		spi-cpol;

		spi-cpha;

		spi-rx-bus-width = <4>;

		#address-cells = <1>;

		#size-cells = <1>;



		partition@0 {

			label = "data";

			reg = <0 0x200000>;

		};

	};

};

drivers/mtd/ftl.c

+1 −1
Original line number Diff line number Diff line
@@ -344,7 +344,7 @@ static int erase_xfer(partition_t *part, 
            return -ENOMEM;



    erase->addr = xfer->Offset;

    erase->len = 1 << part->header.EraseUnitSize;

    erase->len = 1ULL << part->header.EraseUnitSize;



    ret = mtd_erase(part->mbd.mtd, erase);

    if (!ret) {

drivers/mtd/nand/raw/atmel/nand-controller.c

+1 −1
Original line number Diff line number Diff line
@@ -373,7 +373,7 @@ static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc, 
	dma_cookie_t cookie;



	buf_dma = dma_map_single(nc->dev, buf, len, dir);

	if (dma_mapping_error(nc->dev, dev_dma)) {

	if (dma_mapping_error(nc->dev, buf_dma)) {

		dev_err(nc->dev,

			"Failed to prepare a buffer for DMA access\n");

		goto err;