Commit ccaba800 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools headers x86 cpufeatures: Sync with the kernel sources 



To pick the changes from:

  e19c0621 ("x86/cpufeatures: Add support for Assignable Bandwidth Monitoring Counters (ABMC)")
  7b59c73f ("x86/cpufeatures: Add SNP Secure TSC")
  3c7cb841 ("x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions")
  2f8f1734 ("x86/vmscape: Add conditional IBPB mitigation")
  a508cec6 ("x86/vmscape: Enumerate VMSCAPE bug")

This causes these perf files to be rebuilt and brings some X86_FEATURE
that may be used by:

      CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
      CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Please see tools/include/uapi/README for further details.

Cc: Babu Moger <babu.moger@amd.com>
Cc: Borislav Petkov (AMD) <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Nikunj A Dadhania <nikunj@amd.com>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Xin Li <xin@zytor.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent e0acec33

tools/arch/x86/include/asm/cpufeatures.h

+5 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ 
#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* VM Page Flush MSR is supported */

#define X86_FEATURE_SEV_ES		(19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_SEV_SNP		(19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */

#define X86_FEATURE_SNP_SECURE_TSC	(19*32+ 8) /* SEV-SNP Secure TSC */

#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* hardware-enforced cache coherency */

#define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
@@ -495,6 +496,9 @@ 
#define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */

#define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */

#define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */

#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */

#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */

#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */



/*

 * BUG word(s)
@@ -551,4 +555,5 @@ 
#define X86_BUG_ITS			X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indirect Target Selection */

#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX is not affected */

#define X86_BUG_TSA			X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */

#define X86_BUG_VMSCAPE			X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */

#endif /* _ASM_X86_CPUFEATURES_H */