Unverified Commit cd1a5162 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Rodrigo Vivi
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drm/xe/xelp: Wait for AuxCCS invalidation to complete 



On AuxCCS platforms we need to wait for AuxCCS invalidations to complete.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260324084018.20353-6-tvrtko.ursulin@igalia.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 458b1e64

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

+6 −0
Original line number Diff line number Diff line
@@ -94,4 +94,10 @@ 
#define MI_SET_APPID_SESSION_ID_MASK	REG_GENMASK(6, 0)

#define MI_SET_APPID_SESSION_ID(x)	REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)



#define MI_SEMAPHORE_WAIT_TOKEN		(__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */

#define   MI_SEMAPHORE_REGISTER_POLL	REG_BIT(16)

#define   MI_SEMAPHORE_POLL		REG_BIT(15)

#define   MI_SEMAPHORE_CMP_OP_MASK	REG_GENMASK(14, 12)

#define   MI_SEMAPHORE_SAD_EQ_SDD	REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4)



#endif

drivers/gpu/drm/xe/xe_ring_ops.c

+8 −1
Original line number Diff line number Diff line
@@ -54,7 +54,14 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg, 
	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;

	dw[i++] = reg.addr + gt->mmio.adj_offset;

	dw[i++] = AUX_INV;

	dw[i++] = MI_NOOP;

	dw[i++] = MI_SEMAPHORE_WAIT_TOKEN |

		  MI_SEMAPHORE_REGISTER_POLL |

		  MI_SEMAPHORE_POLL |

		  MI_SEMAPHORE_SAD_EQ_SDD;

	dw[i++] = 0;

	dw[i++] = reg.addr + gt->mmio.adj_offset;

	dw[i++] = 0;

	dw[i++] = 0;



	return i;

}

drivers/gpu/drm/xe/xe_ring_ops_types.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


struct xe_sched_job;



#define MAX_JOB_SIZE_DW 72

#define MAX_JOB_SIZE_DW 74

#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)



/**