Unverified Commit cddd6386 authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
Browse files

riscv: Add thead and xtheadvector as a vendor extension 



Add support to the kernel for THead vendor extensions with the target of
the new extension xtheadvector.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ce1daeeb

arch/riscv/Kconfig.vendor

+13 −0
Original line number Diff line number Diff line
@@ -16,4 +16,17 @@ config RISCV_ISA_VENDOR_EXT_ANDES 
	  If you don't know what to do here, say Y.

endmenu



menu "T-Head"

config RISCV_ISA_VENDOR_EXT_THEAD

	bool "T-Head vendor extension support"

	select RISCV_ISA_VENDOR_EXT

	default y

	help

	  Say N here to disable detection of and support for all T-Head vendor

	  extensions. Without this option enabled, T-Head vendor extensions will

	  not be detected at boot and their presence not reported to userspace.



	  If you don't know what to do here, say Y.

endmenu



endmenu

arch/riscv/include/asm/vendor_extensions/thead.h

0 → 100644
+16 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H

#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H



#include <asm/vendor_extensions.h>



#include <linux/types.h>



/*

 * Extension keys must be strictly less than RISCV_ISA_VENDOR_EXT_MAX.

 */

#define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR		0



extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead;



#endif

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <asm/sbi.h>

#include <asm/vector.h>

#include <asm/vendor_extensions.h>

#include <asm/vendor_extensions/thead.h>



#define NUM_ALPHA_EXTS ('z' - 'a' + 1)

arch/riscv/kernel/vendor_extensions.c

+10 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <asm/vendorid_list.h>

#include <asm/vendor_extensions.h>

#include <asm/vendor_extensions/andes.h>

#include <asm/vendor_extensions/thead.h>



#include <linux/array_size.h>

#include <linux/types.h>
@@ -14,6 +15,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { 
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES

	&riscv_isa_vendor_ext_list_andes,

#endif

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD

	&riscv_isa_vendor_ext_list_thead,

#endif

};



const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list);
@@ -41,6 +45,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig 
		cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;

		break;

	#endif

	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD

	case THEAD_VENDOR_ID:

		bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap;

		cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap;

		break;

	#endif

	default:

		return false;

	}

arch/riscv/kernel/vendor_extensions/Makefile

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only



obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o